Add new builtin FF types

[yosys.git] / passes / cmds / scatter.cc

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index cd1b3286f7baf2d22ea04fdf10c5a66ee7fa45cb..a70dd308602877a4dc40e1ddacc35b69724c9b71 100644 (file)
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct ScatterPass : public Pass {
        ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -41,7 +41,7 @@ struct ScatterPass : public Pass {
                log("Use the opt_clean command to get rid of the additional nets.\n");
                log("\n");
        }
-       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::vector<std::string> args, RTLIL::Design *design) override
        {
                CellTypes ct(design);
                extra_args(args, 1, design);
@@ -49,9 +49,9 @@ struct ScatterPass : public Pass {
                for (auto module : design->selected_modules())
                {
                        for (auto cell : module->cells()) {
-                               std::map<RTLIL::IdString, std::pair<RTLIL::SigSpec, RTLIL::SigSpec>> new_connections;
+                               dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
                                for (auto conn : cell->connections())
-                                       new_connections.emplace(conn.first, std::make_pair(conn.second, module->addWire(NEW_ID, conn.second.size())));
+                                       new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
                                for (auto &it : new_connections) {
                                        if (ct.cell_output(cell->type, it.first))
                                                module->connect(RTLIL::SigSig(it.second.first, it.second.second));