new_wire_name += format.substr(0, 1);
if (width > 1) {
- new_wire_name += stringf("%d", offset+width-1);
+ if (wire->upto)
+ new_wire_name += stringf("%d", wire->start_offset+wire->width-(offset+width)-1);
+ else
+ new_wire_name += stringf("%d", wire->start_offset+offset+width-1);
if (format.size() > 2)
new_wire_name += format.substr(2, 1);
else
new_wire_name += ":";
}
- new_wire_name += stringf("%d", offset);
+ if (wire->upto)
+ new_wire_name += stringf("%d", wire->start_offset+wire->width-offset-1);
+ else
+ new_wire_name += stringf("%d", wire->start_offset+offset);
if (format.size() > 1)
new_wire_name += format.substr(1, 1);
new_wire->port_id = wire->port_id ? wire->port_id + offset : 0;
new_wire->port_input = wire->port_input;
new_wire->port_output = wire->port_output;
+ new_wire->start_offset = wire->start_offset + offset;
+
+ auto it = wire->attributes.find(ID::src);
+ if (it != wire->attributes.end())
+ new_wire->attributes.emplace(ID::src, it->second);
- if (wire->attributes.count("\\src"))
- new_wire->attributes["\\src"] = wire->attributes.at("\\src");
+ it = wire->attributes.find(ID::hdlname);
+ if (it != wire->attributes.end())
+ new_wire->attributes.emplace(ID::hdlname, it->second);
- if (wire->attributes.count("\\keep"))
- new_wire->attributes["\\keep"] = wire->attributes.at("\\keep");
+ it = wire->attributes.find(ID::keep);
+ if (it != wire->attributes.end())
+ new_wire->attributes.emplace(ID::keep, it->second);
- if (wire->attributes.count("\\init")) {
- Const old_init = wire->attributes.at("\\init"), new_init;
+ it = wire->attributes.find(ID::init);
+ if (it != wire->attributes.end()) {
+ Const old_init = it->second, new_init;
for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
- new_wire->attributes["\\init"] = new_init;
+ new_wire->attributes.emplace(ID::init, new_init);
}
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
struct SplitnetsPass : public Pass {
SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
- virtual void help()
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" and split nets so that no driver drives only part of a net.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_ports = false;
bool flag_driver = false;
for (auto module : design->selected_modules())
{
+ if (module->has_processes_warn())
+ continue;
+
SplitnetsWorker worker;
if (flag_ports)
std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
- for (auto &c : module->cells_)
- for (auto &p : c.second->connections())
+ for (auto c : module->cells())
+ for (auto &p : c->connections())
{
- if (!ct.cell_known(c.second->type))
+ if (!ct.cell_known(c->type))
continue;
- if (!ct.cell_output(c.second->type, p.first))
+ if (!ct.cell_output(c->type, p.first))
continue;
RTLIL::SigSpec sig = p.second;
}
else
{
- for (auto &w : module->wires_) {
- RTLIL::Wire *wire = w.second;
- if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
+ for (auto wire : module->wires()) {
+ if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
}