Merge pull request #2168 from whitequark/assert-unused-exprs

[yosys.git] / passes / cmds / splitnets.cc

diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index de275874f6fb11c3287e974f36404db49f362340..fff8a0d3efad0e2a55c97ff9dcb9f67b0f7eece9 100644 (file)
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -61,20 +61,24 @@ struct SplitnetsWorker
                new_wire->port_output = wire->port_output;
                new_wire->start_offset = wire->start_offset + offset;
 
-               if (wire->attributes.count(ID::src))
-                       new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
+               auto it = wire->attributes.find(ID::src);
+               if (it != wire->attributes.end())
+                       new_wire->attributes.emplace(ID::src, it->second);
 
-               if (wire->attributes.count(ID::hdlname))
-                       new_wire->attributes[ID::hdlname] = wire->attributes.at(ID::hdlname);
+               it = wire->attributes.find(ID::hdlname);
+               if (it != wire->attributes.end())
+                       new_wire->attributes.emplace(ID::hdlname, it->second);
 
-               if (wire->attributes.count(ID::keep))
-                       new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep);
+               it = wire->attributes.find(ID::keep);
+               if (it != wire->attributes.end())
+                       new_wire->attributes.emplace(ID::keep, it->second);
 
-               if (wire->attributes.count(ID::init)) {
-                       Const old_init = wire->attributes.at(ID::init), new_init;
+               it = wire->attributes.find(ID::init);
+               if (it != wire->attributes.end()) {
+                       Const old_init = it->second, new_init;
                        for (int i = offset; i < offset+width; i++)
                                new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
-                       new_wire->attributes[ID::init] = new_init;
+                       new_wire->attributes.emplace(ID::init, new_init);
                }
 
                std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
@@ -91,7 +95,7 @@ struct SplitnetsWorker
 
 struct SplitnetsPass : public Pass {
        SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -113,7 +117,7 @@ struct SplitnetsPass : public Pass {
                log("        and split nets so that no driver drives only part of a net.\n");
                log("\n");
        }
-       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::vector<std::string> args, RTLIL::Design *design) override
        {
                bool flag_ports = false;
                bool flag_driver = false;
@@ -170,12 +174,12 @@ struct SplitnetsPass : public Pass {
 
                                std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
 
-                               for (auto &c : module->cells_)
-                               for (auto &p : c.second->connections())
+                               for (auto c : module->cells())
+                               for (auto &p : c->connections())
                                {
-                                       if (!ct.cell_known(c.second->type))
+                                       if (!ct.cell_known(c->type))
                                                continue;
-                                       if (!ct.cell_output(c.second->type, p.first))
+                                       if (!ct.cell_output(c->type, p.first))
                                                continue;
 
                                        RTLIL::SigSpec sig = p.second;
@@ -202,9 +206,8 @@ struct SplitnetsPass : public Pass {
                        }
                        else
                        {
-                               for (auto &w : module->wires_) {
-                                       RTLIL::Wire *wire = w.second;
-                                       if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
+                               for (auto wire : module->wires()) {
+                                       if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
                                                worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
                                }