Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim

[yosys.git] / passes / equiv / equiv_miter.cc

diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index 23b348184dac672be5ae63a6eb5f3f46dfc5edf1..e06f9515b32ec0384e072b6775cc1c6686f0523d 100644 (file)
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -156,7 +156,7 @@ struct EquivMiterWorker
                struct RewriteSigSpecWorker {
                        RTLIL::Module * mod;
                        void operator()(SigSpec &sig) {
-                               vector<RTLIL::SigChunk> chunks = sig.chunks();
+                               vector<SigChunk> chunks = sig.chunks();
                                for (auto &c : chunks)
                                        if (c.wire != NULL)
                                                c.wire = mod->wires_.at(c.wire->name);
@@ -261,7 +261,7 @@ struct EquivMiterWorker
 
 struct EquivMiterPass : public Pass {
        EquivMiterPass() : Pass("equiv_miter", "extract miter from equiv circuit") { }
-       virtual void help()
+       void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -282,7 +282,7 @@ struct EquivMiterPass : public Pass {
                log("        Create compare logic that handles undefs correctly\n");
                log("\n");
        }
-       virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
                EquivMiterWorker worker;
                worker.ct.setup(design);
@@ -333,7 +333,7 @@ struct EquivMiterPass : public Pass {
        found_two_modules:
                        log_cmd_error("Exactly one module must be selected for 'equiv_miter'!\n");
 
-               log_header("Executing EQUIV_MITER pass.\n");
+               log_header(design, "Executing EQUIV_MITER pass.\n");
 
                worker.miter_module = design->addModule(worker.miter_name);
                worker.run();