log("\n");
log(" equiv_opt [options] [command]\n");
log("\n");
- log("This command checks circuit equivalence before and after an optimization pass.\n");
+ log("This command uses temporal induction to check circuit equivalence before and\n");
+ log("after an optimization pass.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" -multiclock\n");
log(" run clk2fflogic before equivalence checking.\n");
log("\n");
+ log(" -async2sync\n");
+ log(" run async2sync before equivalence checking.\n");
+ log("\n");
log(" -undef\n");
log(" enable modelling of undef states during equiv_induct.\n");
log("\n");
if (multiclock || help_mode)
run("clk2fflogic", "(only with -multiclock)");
if (async2sync || help_mode)
- run("async2sync", "(only with -async2sync)");
+ run("async2sync", " (only with -async2sync)");
run("equiv_make gold gate equiv");
if (help_mode)
run("equiv_induct [-undef] equiv");