Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim

[yosys.git] / passes / equiv / equiv_opt.cc

diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index d13e46ce47d53858d7102d4933470261ef4a08e0..c7e6d71a62e2a69a9794cc6f3056e2403fbd0dd0 100644 (file)
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -32,7 +32,8 @@ struct EquivOptPass:public ScriptPass
                log("\n");
                log("    equiv_opt [options] [command]\n");
                log("\n");
-               log("This command checks circuit equivalence before and after an optimization pass.\n");
+               log("This command uses temporal induction to check circuit equivalence before and\n");
+               log("after an optimization pass.\n");
                log("\n");
                log("    -run <from_label>:<to_label>\n");
                log("        only run the commands between the labels (see below). an empty\n");
@@ -49,6 +50,9 @@ struct EquivOptPass:public ScriptPass
                log("    -multiclock\n");
                log("        run clk2fflogic before equivalence checking.\n");
                log("\n");
+               log("    -async2sync\n");
+               log("        run async2sync before equivalence checking.\n");
+               log("\n");
                log("    -undef\n");
                log("        enable modelling of undef states during equiv_induct.\n");
                log("\n");
@@ -165,7 +169,7 @@ struct EquivOptPass:public ScriptPass
                        if (multiclock || help_mode)
                                run("clk2fflogic", "(only with -multiclock)");
                        if (async2sync || help_mode)
-                               run("async2sync", "(only with -async2sync)");
+                               run("async2sync", " (only with -async2sync)");
                        run("equiv_make gold gate equiv");
                        if (help_mode)
                                run("equiv_induct [-undef] equiv");