Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim

[yosys.git] / passes / equiv / equiv_opt.cc

diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index ec12004888a2282f71ea1fcddc933457dd51d5f8..c7e6d71a62e2a69a9794cc6f3056e2403fbd0dd0 100644 (file)
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -50,6 +50,9 @@ struct EquivOptPass:public ScriptPass
                log("    -multiclock\n");
                log("        run clk2fflogic before equivalence checking.\n");
                log("\n");
+               log("    -async2sync\n");
+               log("        run async2sync before equivalence checking.\n");
+               log("\n");
                log("    -undef\n");
                log("        enable modelling of undef states during equiv_induct.\n");
                log("\n");
@@ -166,7 +169,7 @@ struct EquivOptPass:public ScriptPass
                        if (multiclock || help_mode)
                                run("clk2fflogic", "(only with -multiclock)");
                        if (async2sync || help_mode)
-                               run("async2sync", "(only with -async2sync)");
+                               run("async2sync", " (only with -async2sync)");
                        run("equiv_make gold gate equiv");
                        if (help_mode)
                                run("equiv_induct [-undef] equiv");