Merge remote-tracking branch 'upstream/master'

[yosys.git] / passes / fsm / fsmdata.h

diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 7a44dd4522875d53b8bf8bc24af112de383157e9..68222769a524301bf3165f82e8a05b69e5c3ea36 100644 (file)
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -20,8 +20,9 @@
 #ifndef FSMDATA_H
 #define FSMDATA_H
 
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
 
 struct FsmData
 {
@@ -38,7 +39,7 @@ struct FsmData
                int state_num_log2 = 0;
                for (int i = state_table.size(); i > 0; i = i >> 1)
                        state_num_log2++;
-               state_num_log2 = std::max(state_num_log2, 1);
+               state_num_log2 = max(state_num_log2, 1);
 
                cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits);
                cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size());
@@ -142,24 +143,24 @@ struct FsmData
                log("\n");
                log("  Input signals:\n");
                RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
-               for (int i = 0; i < SIZE(sig_in); i++)
+               for (int i = 0; i < GetSize(sig_in); i++)
                        log("  %3d: %s\n", i, log_signal(sig_in[i]));
 
                log("\n");
                log("  Output signals:\n");
                RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
-               for (int i = 0; i < SIZE(sig_out); i++)
+               for (int i = 0; i < GetSize(sig_out); i++)
                        log("  %3d: %s\n", i, log_signal(sig_out[i]));
 
                log("\n");
                log("  State encoding:\n");
-               for (int i = 0; i < SIZE(state_table); i++)
+               for (int i = 0; i < GetSize(state_table); i++)
                        log("  %3d: %10s%s\n", i, log_signal(state_table[i], false),
                                        int(i) == reset_state ? "  <RESET STATE>" : "");
 
                log("\n");
                log("  Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n");
-               for (int i = 0; i < SIZE(transition_table); i++) {
+               for (int i = 0; i < GetSize(transition_table); i++) {
                        transition_t &tr = transition_table[i];
                        log("  %5d: %5d %s   -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
                }
@@ -172,4 +173,6 @@ struct FsmData
        static void optimize_fsm(RTLIL::Cell *cell, RTLIL::Module *module);
 };
 
+YOSYS_NAMESPACE_END
+
 #endif