SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim...

[yosys.git] / passes / hierarchy / submod.cc

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 7d081125482cc946f23a6750ff0d8630dcfcfe08..b983a840e6a3eefe31b3389802767c2704473ea8 100644 (file)
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -67,7 +67,7 @@ struct SubmodWorker
 
        void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
        {
-               for (auto &c : sig.chunks)
+               for (auto &c : sig.chunks())
                        if (c.wire != NULL)
                                flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
        }
@@ -164,7 +164,7 @@ struct SubmodWorker
                for (RTLIL::Cell *cell : submod.cells) {
                        RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
                        for (auto &conn : new_cell->connections)
-                               for (auto &c : conn.second.chunks)
+                               for (auto &c : conn.second.chunks_rw())
                                        if (c.wire != NULL) {
                                                assert(wire_flags.count(c.wire) > 0);
                                                c.wire = wire_flags[c.wire].new_wire;
@@ -338,7 +338,7 @@ struct SubmodPass : public Pass {
                        if (module == NULL)
                                log("Nothing selected -> do nothing.\n");
                        else {
-                               Pass::call_newsel(design, stringf("opt_clean %s", module->name.c_str()));
+                               Pass::call_on_module(design, module, "opt_clean");
                                log_header("Continuing SUBMOD pass.\n");
                                SubmodWorker worker(design, module, opt_name);
                        }