SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim...

[yosys.git] / passes / memory / memory_dff.cc

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 8bae24cff3b50e3e60c18776ea74937dda4a2e18..dee48597fbef6513b4d212b585425b4a44eb6ef3 100644 (file)
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -36,7 +36,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 
        for (size_t i = 0; i < sig.chunks().size(); i++)
        {
-               RTLIL::SigChunk &chunk = sig.chunks()[i];
+               RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
 
                if (chunk.wire == NULL)
                        continue;