/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
*
*/
-#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
+#include "kernel/satgen.h"
#include "kernel/sigtools.h"
-#include "kernel/register.h"
-#include "kernel/log.h"
-#include <algorithm>
+#include "kernel/modtools.h"
+#include "kernel/mem.h"
-static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
-{
- if (a->type == "$memrd" && b->type == "$memrd")
- return a->name < b->name;
- if (a->type == "$memrd" || b->type == "$memrd")
- return (a->type == "$memrd") < (b->type == "$memrd");
- return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
-}
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
struct MemoryShareWorker
{
RTLIL::Design *design;
RTLIL::Module *module;
- SigMap sigmap;
-
- RTLIL::SigSpec mask_en_naive(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
- {
- // this is the naive version of the function that does not care about grouping the EN bits.
+ SigMap sigmap, sigmap_xmux;
+ ModWalker modwalker;
+ CellTypes cone_ct;
+ bool flag_widen;
+
+
+ // --------------------------------------------------
+ // Consolidate read ports that read the same address
+ // (or close enough to be merged to wide ports)
+ // --------------------------------------------------
+
+ // A simple function to detect ports that couldn't possibly collide
+ // because of opposite const address bits (simplistic, but enough
+ // to fix problems with inferring wide ports).
+ bool rdwr_can_collide(Mem &mem, int ridx, int widx) {
+ auto &rport = mem.rd_ports[ridx];
+ auto &wport = mem.wr_ports[widx];
+ for (int i = std::max(rport.wide_log2, wport.wide_log2); i < GetSize(rport.addr) && i < GetSize(wport.addr); i++) {
+ if (rport.addr[i] == State::S1 && wport.addr[i] == State::S0)
+ return false;
+ if (rport.addr[i] == State::S0 && wport.addr[i] == State::S1)
+ return false;
+ }
+ return true;
+ }
- RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits);
- RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.width), inv_mask_bits, do_mask);
- RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits);
- return result;
+ bool merge_rst_value(Mem &mem, Const &res, int wide_log2, const Const &src1, int sub1, const Const &src2, int sub2) {
+ res = Const(State::Sx, mem.width << wide_log2);
+ for (int i = 0; i < GetSize(src1); i++)
+ res[i + sub1 * mem.width] = src1[i];
+ for (int i = 0; i < GetSize(src2); i++) {
+ if (src2[i] == State::Sx)
+ continue;
+ auto &dst = res[i + sub2 * mem.width];
+ if (dst == src2[i])
+ continue;
+ if (dst != State::Sx)
+ return false;
+ dst = src2[i];
+ }
+ return true;
}
- RTLIL::SigSpec mask_en_grouped(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
+ bool consolidate_rd_by_addr(Mem &mem)
{
- // this version of the function preserves the bit grouping in the EN bits.
-
- std::vector<RTLIL::SigBit> v_bits = bits;
- std::vector<RTLIL::SigBit> v_mask_bits = mask_bits;
+ if (GetSize(mem.rd_ports) <= 1)
+ return false;
- std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups;
- RTLIL::SigSpec grouped_bits, grouped_mask_bits;
+ log("Consolidating read ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
- for (int i = 0; i < bits.width; i++) {
- std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
- if (groups.count(key) == 0) {
- groups[key].first = grouped_bits.width;
- grouped_bits.append_bit(v_bits[i]);
- grouped_mask_bits.append_bit(v_mask_bits[i]);
+ bool changed = false;
+ for (int i = 0; i < GetSize(mem.rd_ports); i++)
+ {
+ auto &port1 = mem.rd_ports[i];
+ if (port1.removed)
+ continue;
+ for (int j = i + 1; j < GetSize(mem.rd_ports); j++)
+ {
+ auto &port2 = mem.rd_ports[j];
+ if (port2.removed)
+ continue;
+ if (port1.clk_enable != port2.clk_enable)
+ continue;
+ if (port1.clk_enable) {
+ if (port1.clk != port2.clk)
+ continue;
+ if (port1.clk_polarity != port2.clk_polarity)
+ continue;
+ }
+ if (port1.en != port2.en)
+ continue;
+ if (port1.arst != port2.arst)
+ continue;
+ if (port1.srst != port2.srst)
+ continue;
+ if (port1.ce_over_srst != port2.ce_over_srst)
+ continue;
+ if (port1.transparent != port2.transparent)
+ continue;
+ // If the width of the ports doesn't match, they can still be
+ // merged by widening the narrow one. Check if the conditions
+ // hold for that.
+ int wide_log2 = std::max(port1.wide_log2, port2.wide_log2);
+ if (GetSize(port1.addr) <= wide_log2)
+ continue;
+ if (GetSize(port2.addr) <= wide_log2)
+ continue;
+ if (!port1.addr.extract(0, wide_log2).is_fully_const())
+ continue;
+ if (!port2.addr.extract(0, wide_log2).is_fully_const())
+ continue;
+ if (sigmap_xmux(port1.addr.extract_end(wide_log2)) != sigmap_xmux(port2.addr.extract_end(wide_log2))) {
+ // Incompatible addresses after widening. Last chance — widen both
+ // ports by one more bit to merge them.
+ if (!flag_widen)
+ continue;
+ wide_log2++;
+ if (sigmap_xmux(port1.addr.extract_end(wide_log2)) != sigmap_xmux(port2.addr.extract_end(wide_log2)))
+ continue;
+ if (!port1.addr.extract(0, wide_log2).is_fully_const())
+ continue;
+ if (!port2.addr.extract(0, wide_log2).is_fully_const())
+ continue;
+ }
+ // Combine init/reset values.
+ SigSpec sub1_c = port1.addr.extract(0, wide_log2);
+ log_assert(sub1_c.is_fully_const());
+ int sub1 = sub1_c.as_int();
+ SigSpec sub2_c = port2.addr.extract(0, wide_log2);
+ log_assert(sub2_c.is_fully_const());
+ int sub2 = sub2_c.as_int();
+ Const init_value, arst_value, srst_value;
+ if (!merge_rst_value(mem, init_value, wide_log2, port1.init_value, sub1, port2.init_value, sub2))
+ continue;
+ if (!merge_rst_value(mem, arst_value, wide_log2, port1.arst_value, sub1, port2.arst_value, sub2))
+ continue;
+ if (!merge_rst_value(mem, srst_value, wide_log2, port1.srst_value, sub1, port2.srst_value, sub2))
+ continue;
+ {
+ log(" Merging ports %d, %d (address %s).\n", i, j, log_signal(port1.addr));
+ mem.widen_prep(wide_log2);
+ SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2);
+ module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2));
+ module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2));
+ port1.addr = sigmap_xmux(port1.addr);
+ for (int k = 0; k < wide_log2; k++)
+ port1.addr[k] = State::S0;
+ port1.init_value = init_value;
+ port1.arst_value = arst_value;
+ port1.srst_value = srst_value;
+ port1.wide_log2 = wide_log2;
+ port1.data = new_data;
+ port2.removed = true;
+ changed = true;
+ }
}
- groups[key].second.push_back(i);
}
- std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits);
- RTLIL::SigSpec result;
-
- for (int i = 0; i < bits.width; i++) {
- std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
- result.append_bit(grouped_result.at(groups.at(key).first));
- }
+ if (changed)
+ mem.emit();
- return result;
+ return changed;
}
- void merge_en_data(RTLIL::SigSpec &merged_en, RTLIL::SigSpec &merged_data, RTLIL::SigSpec next_en, RTLIL::SigSpec next_data)
+
+ // ------------------------------------------------------
+ // Consolidate write ports that write to the same address
+ // (or close enough to be merged to wide ports)
+ // ------------------------------------------------------
+
+ bool consolidate_wr_by_addr(Mem &mem)
{
- std::vector<RTLIL::SigBit> v_old_en = merged_en;
- std::vector<RTLIL::SigBit> v_next_en = next_en;
-
- // The new merged_en signal is just the old merged_en signal and next_en OR'ed together.
- // But of course we need to preserve the bit grouping..
-
- std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups;
- std::vector<RTLIL::SigBit> grouped_old_en, grouped_next_en;
- RTLIL::SigSpec new_merged_en;
-
- for (int i = 0; i < int(v_old_en.size()); i++) {
- std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
- if (groups.count(key) == 0) {
- groups[key] = grouped_old_en.size();
- grouped_old_en.push_back(key.first);
- grouped_next_en.push_back(key.second);
- }
- }
+ if (GetSize(mem.wr_ports) <= 1)
+ return false;
- std::vector<RTLIL::SigBit> grouped_new_en = module->Or(NEW_ID, grouped_old_en, grouped_next_en);
+ log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
- for (int i = 0; i < int(v_old_en.size()); i++) {
- std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
- new_merged_en.append_bit(grouped_new_en.at(groups.at(key)));
+ bool changed = false;
+ for (int i = 0; i < GetSize(mem.wr_ports); i++)
+ {
+ auto &port1 = mem.wr_ports[i];
+ if (port1.removed)
+ continue;
+ if (!port1.clk_enable)
+ continue;
+ for (int j = i + 1; j < GetSize(mem.wr_ports); j++)
+ {
+ auto &port2 = mem.wr_ports[j];
+ if (port2.removed)
+ continue;
+ if (!port2.clk_enable)
+ continue;
+ if (port1.clk != port2.clk)
+ continue;
+ if (port1.clk_polarity != port2.clk_polarity)
+ continue;
+ // If the width of the ports doesn't match, they can still be
+ // merged by widening the narrow one. Check if the conditions
+ // hold for that.
+ int wide_log2 = std::max(port1.wide_log2, port2.wide_log2);
+ if (GetSize(port1.addr) <= wide_log2)
+ continue;
+ if (GetSize(port2.addr) <= wide_log2)
+ continue;
+ if (!port1.addr.extract(0, wide_log2).is_fully_const())
+ continue;
+ if (!port2.addr.extract(0, wide_log2).is_fully_const())
+ continue;
+ if (sigmap_xmux(port1.addr.extract_end(wide_log2)) != sigmap_xmux(port2.addr.extract_end(wide_log2))) {
+ // Incompatible addresses after widening. Last chance — widen both
+ // ports by one more bit to merge them.
+ if (!flag_widen)
+ continue;
+ wide_log2++;
+ if (sigmap_xmux(port1.addr.extract_end(wide_log2)) != sigmap_xmux(port2.addr.extract_end(wide_log2)))
+ continue;
+ if (!port1.addr.extract(0, wide_log2).is_fully_const())
+ continue;
+ if (!port2.addr.extract(0, wide_log2).is_fully_const())
+ continue;
+ }
+ log(" Merging ports %d, %d (address %s).\n", i, j, log_signal(port1.addr));
+ mem.prepare_wr_merge(i, j);
+ port1.addr = sigmap_xmux(port1.addr);
+ port2.addr = sigmap_xmux(port2.addr);
+ mem.widen_wr_port(i, wide_log2);
+ mem.widen_wr_port(j, wide_log2);
+ int pos = 0;
+ while (pos < GetSize(port1.data)) {
+ int epos = pos;
+ while (epos < GetSize(port1.data) && port1.en[epos] == port1.en[pos] && port2.en[epos] == port2.en[pos])
+ epos++;
+ int width = epos - pos;
+ SigBit new_en;
+ if (port2.en[pos] == State::S0) {
+ new_en = port1.en[pos];
+ } else if (port1.en[pos] == State::S0) {
+ port1.data.replace(pos, port2.data.extract(pos, width));
+ new_en = port2.en[pos];
+ } else {
+ port1.data.replace(pos, module->Mux(NEW_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos]));
+ new_en = module->Or(NEW_ID, port1.en[pos], port2.en[pos]);
+ }
+ for (int k = pos; k < epos; k++)
+ port1.en[k] = new_en;
+ pos = epos;
+ }
+ changed = true;
+ port2.removed = true;
+ }
}
- // Create the new merged_data signal.
+ if (changed)
+ mem.emit();
- RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.width);
+ return changed;
+ }
- RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data);
- RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data));
- RTLIL::SigSpec new_data_set = module->And(NEW_ID, next_en, next_data);
- RTLIL::SigSpec new_data_unset = module->And(NEW_ID, next_en, module->Not(NEW_ID, next_data));
+ // --------------------------------------------------------
+ // Consolidate write ports using sat-based resource sharing
+ // --------------------------------------------------------
- new_merged_data = module->Or(NEW_ID, new_merged_data, old_data_set);
- new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, old_data_unset));
+ void consolidate_wr_using_sat(Mem &mem)
+ {
+ if (GetSize(mem.wr_ports) <= 1)
+ return;
- new_merged_data = module->Or(NEW_ID, new_merged_data, new_data_set);
- new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, new_data_unset));
+ // Get a list of ports that have any chance of being mergeable.
- // Update merged_* signals
+ pool<int> eligible_ports;
- merged_en = new_merged_en;
- merged_data = new_merged_data;
- }
+ for (int i = 0; i < GetSize(mem.wr_ports); i++) {
+ auto &port = mem.wr_ports[i];
+ std::vector<RTLIL::SigBit> bits = modwalker.sigmap(port.en);
+ for (auto bit : bits)
+ if (bit == RTLIL::State::S1)
+ goto port_is_always_active;
+ eligible_ports.insert(i);
+ port_is_always_active:;
+ }
- void consolidate_wr_by_addr(std::string memid, std::vector<RTLIL::Cell*> &wr_ports)
- {
- log("Consolidating write ports of memory %s by address:\n", log_id(memid));
+ if (eligible_ports.size() <= 1)
+ return;
- std::map<RTLIL::SigSpec, int> last_port_by_addr;
- std::vector<std::vector<bool>> active_bits_on_port;
+ log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(mem.memid));
- bool cache_clk_enable = false;
- bool cache_clk_polarity = false;
- RTLIL::SigSpec cache_clk;
+ // Group eligible ports by clock domain and width.
- for (int i = 0; i < int(wr_ports.size()); i++)
+ pool<int> checked_ports;
+ std::vector<std::vector<int>> groups;
+ for (int i = 0; i < GetSize(mem.wr_ports); i++)
{
- RTLIL::Cell *cell = wr_ports.at(i);
- RTLIL::SigSpec addr = sigmap(cell->connections.at("\\ADDR"));
+ auto &port1 = mem.wr_ports[i];
+ if (!eligible_ports.count(i))
+ continue;
+ if (checked_ports.count(i))
+ continue;
+
+ std::vector<int> group;
+ group.push_back(i);
- if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
- (cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk ||
- cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
+ for (int j = i + 1; j < GetSize(mem.wr_ports); j++)
{
- cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
- cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
- cache_clk = sigmap(cell->connections.at("\\CLK"));
- last_port_by_addr.clear();
-
- if (cache_clk_enable)
- log(" New clock domain: %s %s\n", cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk));
- else
- log(" New clock domain: unclocked\n");
+ auto &port2 = mem.wr_ports[j];
+ if (!eligible_ports.count(j))
+ continue;
+ if (checked_ports.count(j))
+ continue;
+ if (port1.clk_enable != port2.clk_enable)
+ continue;
+ if (port1.clk_enable) {
+ if (port1.clk != port2.clk)
+ continue;
+ if (port1.clk_polarity != port2.clk_polarity)
+ continue;
+ }
+ if (port1.wide_log2 != port2.wide_log2)
+ continue;
+ group.push_back(j);
}
- log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
+ for (auto j : group)
+ checked_ports.insert(j);
+
+ if (group.size() <= 1)
+ continue;
+
+ groups.push_back(group);
+ }
+
+ bool changed = false;
+ for (auto &group : groups) {
+ auto &some_port = mem.wr_ports[group[0]];
+ string ports;
+ for (auto idx : group) {
+ if (idx != group[0])
+ ports += ", ";
+ ports += std::to_string(idx);
+ }
+ if (!some_port.clk_enable) {
+ log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports.c_str());
+ } else {
+ log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports.c_str());
+ }
+
+ // Okay, time to actually run the SAT solver.
+
+ ezSatPtr ez;
+ SatGen satgen(ez.get(), &modwalker.sigmap);
+
+ // create SAT representation of common input cone of all considered EN signals
+
+ pool<Wire*> one_hot_wires;
+ std::set<RTLIL::Cell*> sat_cells;
+ std::set<RTLIL::SigBit> bits_queue;
+ dict<int, int> port_to_sat_variable;
- log(" Active bits: ");
- std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections.at("\\EN"));
- active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
- for (int k = int(en_bits.size())-1; k >= 0; k--) {
- active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
- log("%c", active_bits_on_port[i][k] ? '1' : '0');
+ for (auto idx : group) {
+ RTLIL::SigSpec sig = modwalker.sigmap(mem.wr_ports[idx].en);
+ port_to_sat_variable[idx] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
+
+ std::vector<RTLIL::SigBit> bits = sig;
+ bits_queue.insert(bits.begin(), bits.end());
}
- log("\n");
- if (last_port_by_addr.count(addr))
+ while (!bits_queue.empty())
{
- int last_i = last_port_by_addr.at(addr);
- log(" Merging port %d into this one.\n", last_i);
-
- bool found_overlapping_bits = false;
- for (int k = 0; k < int(en_bits.size()); k++) {
- if (active_bits_on_port[i][k] && active_bits_on_port[last_i][k])
- found_overlapping_bits = true;
- active_bits_on_port[i][k] = active_bits_on_port[i][k] || active_bits_on_port[last_i][k];
- }
+ for (auto bit : bits_queue)
+ if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
+ one_hot_wires.insert(bit.wire);
+
+ pool<ModWalker::PortBit> portbits;
+ modwalker.get_drivers(portbits, bits_queue);
+ bits_queue.clear();
+
+ for (auto &pbit : portbits)
+ if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
+ pool<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell];
+ bits_queue.insert(cell_inputs.begin(), cell_inputs.end());
+ sat_cells.insert(pbit.cell);
+ }
+ }
- // Force this ports addr input to addr directly (skip don't care muxes)
+ for (auto wire : one_hot_wires) {
+ log(" Adding one-hot constraint for wire %s.\n", log_id(wire));
+ vector<int> ez_wire_bits = satgen.importSigSpec(wire);
+ for (int i : ez_wire_bits)
+ for (int j : ez_wire_bits)
+ if (i != j) ez->assume(ez->NOT(i), j);
+ }
- cell->connections.at("\\ADDR") = addr;
+ log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
- // If any of the ports between `last_i' and `i' write to the same address, this
- // will have priority over whatever `last_i` wrote. So we need to revisit those
- // ports and mask the EN bits accordingly.
+ for (auto cell : sat_cells)
+ satgen.importCell(cell);
- RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections.at("\\EN"));
+ log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez->numCnfVariables(), ez->numCnfClauses());
- for (int j = last_i+1; j < i; j++)
- {
- if (wr_ports[j] == NULL)
- continue;
+ // now try merging the ports.
- for (int k = 0; k < int(en_bits.size()); k++)
- if (active_bits_on_port[i][k] && active_bits_on_port[j][k])
- goto found_overlapping_bits_i_j;
+ for (int ii = 0; ii < GetSize(group); ii++) {
+ int idx1 = group[ii];
+ auto &port1 = mem.wr_ports[idx1];
+ if (port1.removed)
+ continue;
+ for (int jj = ii + 1; jj < GetSize(group); jj++) {
+ int idx2 = group[jj];
+ auto &port2 = mem.wr_ports[idx2];
+ if (port2.removed)
+ continue;
- if (0) {
- found_overlapping_bits_i_j:
- log(" Creating collosion-detect logic for port %d.\n", j);
- RTLIL::SigSpec is_same_addr = module->new_wire(1, NEW_ID);
- module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr);
- merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN")));
+ if (ez->solve(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2))) {
+ log(" According to SAT solver sharing of port %d with port %d is not possible.\n", idx1, idx2);
+ continue;
}
- }
- // Then we need to merge the (masked) EN and the DATA signals.
- // Note that we intentionally do not use sigmap() on the DATA ports.
-
- RTLIL::SigSpec merged_data = wr_ports[last_i]->connections.at("\\DATA");
- if (found_overlapping_bits) {
- log(" Creating logic for merging DATA and EN ports.\n");
- merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), cell->connections.at("\\DATA"));
- } else {
- for (int k = 0; k < int(en_bits.size()); k++)
- if (!active_bits_on_port[last_i][k]) {
- merged_en.replace(k, cell->connections.at("\\EN").extract(k, 1));
- merged_data.replace(k, cell->connections.at("\\DATA").extract(k, 1));
- }
- merged_en.optimize();
- merged_data.optimize();
- }
+ log(" Merging port %d into port %d.\n", idx2, idx1);
+ mem.prepare_wr_merge(idx1, idx2);
+ port_to_sat_variable.at(idx1) = ez->OR(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2));
- // Connect the new EN and DATA signals and remove the old write port.
+ RTLIL::SigSpec last_addr = port1.addr;
+ RTLIL::SigSpec last_data = port1.data;
+ std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(port1.en);
- cell->connections.at("\\EN") = merged_en;
- cell->connections.at("\\DATA") = merged_data;
+ RTLIL::SigSpec this_addr = port2.addr;
+ RTLIL::SigSpec this_data = port2.data;
+ std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(port2.en);
- module->cells.erase(wr_ports[last_i]->name);
- delete wr_ports[last_i];
- wr_ports[last_i] = NULL;
+ RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
- log(" Active bits: ");
- std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections.at("\\EN"));
- active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
- for (int k = int(en_bits.size())-1; k >= 0; k--)
- log("%c", active_bits_on_port[i][k] ? '1' : '0');
- log("\n");
- }
+ if (GetSize(last_addr) < GetSize(this_addr))
+ last_addr.extend_u0(GetSize(this_addr));
+ else
+ this_addr.extend_u0(GetSize(last_addr));
+
+ port1.addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
+ port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
- last_port_by_addr[addr] = i;
+ std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
+ RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
+ RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
+
+ for (int j = 0; j < int(this_en.size()); j++) {
+ std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
+ if (!groups_en.count(key)) {
+ grouped_last_en.append(last_en[j]);
+ grouped_this_en.append(this_en[j]);
+ groups_en[key] = grouped_en->width;
+ grouped_en->width++;
+ }
+ en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
+ }
+
+ module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
+ port1.en = en;
+
+ port2.removed = true;
+ changed = true;
+ }
+ }
}
+
+ if (changed)
+ mem.emit();
}
- MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) :
- design(design), module(module), sigmap(module)
- {
- std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
- for (auto &it : module->cells)
- {
- RTLIL::Cell *cell = it.second;
+ // -------------
+ // Setup and run
+ // -------------
+
+ MemoryShareWorker(RTLIL::Design *design, bool flag_widen) : design(design), modwalker(design), flag_widen(flag_widen) {}
- if (cell->type == "$memrd")
- memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell);
+ void operator()(RTLIL::Module* module)
+ {
+ std::vector<Mem> memories = Mem::get_selected_memories(module);
- if (cell->type == "$memwr")
- memindex[cell->parameters.at("\\MEMID").decode_string()].second.push_back(cell);
+ this->module = module;
+ sigmap.set(module);
- if (cell->type == "$mux")
+ sigmap_xmux = sigmap;
+ for (auto cell : module->cells())
+ {
+ if (cell->type == ID($mux))
{
- RTLIL::SigSpec sig_a = sigmap(cell->connections.at("\\A"));
- RTLIL::SigSpec sig_b = sigmap(cell->connections.at("\\B"));
+ RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
+ RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
if (sig_a.is_fully_undef())
- sigmap.add(cell->connections.at("\\Y"), sig_b);
+ sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
else if (sig_b.is_fully_undef())
- sigmap.add(cell->connections.at("\\Y"), sig_a);
+ sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
}
}
- for (auto &it : memindex) {
- std::sort(it.second.first.begin(), it.second.first.end(), memcells_cmp);
- std::sort(it.second.second.begin(), it.second.second.end(), memcells_cmp);
- consolidate_wr_by_addr(it.first, it.second.second);
+ for (auto &mem : memories) {
+ while (consolidate_rd_by_addr(mem));
+ while (consolidate_wr_by_addr(mem));
}
+
+ cone_ct.setup_internals();
+ cone_ct.cell_types.erase(ID($mul));
+ cone_ct.cell_types.erase(ID($mod));
+ cone_ct.cell_types.erase(ID($div));
+ cone_ct.cell_types.erase(ID($modfloor));
+ cone_ct.cell_types.erase(ID($divfloor));
+ cone_ct.cell_types.erase(ID($pow));
+ cone_ct.cell_types.erase(ID($shl));
+ cone_ct.cell_types.erase(ID($shr));
+ cone_ct.cell_types.erase(ID($sshl));
+ cone_ct.cell_types.erase(ID($sshr));
+ cone_ct.cell_types.erase(ID($shift));
+ cone_ct.cell_types.erase(ID($shiftx));
+
+ modwalker.setup(module, &cone_ct);
+
+ for (auto &mem : memories)
+ consolidate_wr_using_sat(mem);
}
};
struct MemorySharePass : public Pass {
MemorySharePass() : Pass("memory_share", "consolidate memory ports") { }
- virtual void help()
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log("\n");
log("This pass merges share-able memory ports into single memory ports.\n");
log("\n");
+ log("The following methods are used to consolidate the number of memory ports:\n");
+ log("\n");
+ log(" - When multiple write ports access the same address then this is converted\n");
+ log(" to a single write port with a more complex data and/or enable logic path.\n");
+ log("\n");
+ log(" - When multiple write ports are never accessed at the same time (a SAT\n");
+ log(" solver is used to determine this), then the ports are merged into a single\n");
+ log(" write port.\n");
+ log("\n");
+ log("Note that in addition to the algorithms implemented in this pass, the $memrd\n");
+ log("and $memwr cells are also subject to generic resource sharing passes (and other\n");
+ log("optimizations) such as \"share\" and \"opt_merge\".\n");
+ log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
- log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {
+ log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
+ // TODO: expose when wide ports are actually supported.
+ bool flag_widen = false;
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
- if (design->selected(mod_it.second))
- MemoryShareWorker(design, mod_it.second);
+ MemoryShareWorker msw(design, flag_widen);
+
+ for (auto module : design->selected_modules())
+ msw(module);
}
} MemorySharePass;
+PRIVATE_NAMESPACE_END
projects / yosys.git / blobdiff