Added $assert cell

[yosys.git] / passes / opt / opt_clean.cc

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 2921c92d86b6d423fb38f56b6fb3dd0d763f47f2..051d8dc684d07270409581af6d30686ab5584feb 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -47,7 +47,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
                                wire2driver.insert(sig, cell);
                        }
                }
-               if (cell->type == "$memwr" || cell->get_bool_attribute("\\keep"))
+               if (cell->type == "$memwr" || cell->type == "$assert" || cell->get_bool_attribute("\\keep"))
                        queue.insert(cell);
                unused.insert(cell);
        }