SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim...

[yosys.git] / passes / opt / opt_const.cc

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 1a1f0fe4205cd79efb0a1b59ba157d4357f4bdb8..9b89291b15474e53004ea97c75a4552a09720a55 100644 (file)
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -699,10 +699,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
                        RTLIL::SigSpec a = cell->connections["\\A"]; \
                        assign_map.apply(a); \
                        if (a.is_fully_const()) { \
-                               a.optimize(); \
-                               if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
                                RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
-                               RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \
+                               RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
                                                cell->parameters["\\A_SIGNED"].as_bool(), false, \
                                                cell->parameters["\\Y_WIDTH"].as_int())); \
                                replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
@@ -715,10 +713,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
                        RTLIL::SigSpec b = cell->connections["\\B"]; \
                        assign_map.apply(a), assign_map.apply(b); \
                        if (a.is_fully_const() && b.is_fully_const()) { \
-                               a.optimize(), b.optimize(); \
-                               if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
-                               if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \
-                               RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \
+                               RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
                                                cell->parameters["\\A_SIGNED"].as_bool(), \
                                                cell->parameters["\\B_SIGNED"].as_bool(), \
                                                cell->parameters["\\Y_WIDTH"].as_int())); \