Fix broken CI, check reset even for constants, trim rstmux
[yosys.git] / passes / pmgen / peepopt_dffmux.pmg
index 60a708616243a8a857c0c57f02e0d7930947ff01..bfd155c58ce334b7c12eac0ea7fb449054070466 100644 (file)
@@ -8,21 +8,23 @@ match dff
        select GetSize(port(dff, \D)) > 1
 endmatch
 
+code sigD
+       sigD = port(dff, \D);
+endcode
+
 match rstmux
        select rstmux->type == $mux
        select GetSize(port(rstmux, \Y)) > 1
-       index <SigSpec> port(rstmux, \Y) === port(dff, \D)
+       index <SigSpec> port(rstmux, \Y) === sigD
        choice <IdString> BA {\B, \A}
        select port(rstmux, BA).is_fully_const()
        set rstmuxBA BA
-       optional
+       semioptional
 endmatch
 
 code sigD
        if (rstmux)
                sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
-       else
-               sigD = port(dff, \D);
 endcode
 
 match cemux
@@ -32,76 +34,114 @@ match cemux
        choice <IdString> AB {\A, \B}
        index <SigSpec> port(cemux, AB) === port(dff, \Q)
        set cemuxAB AB
+       semioptional
 endmatch
 
 code
-       SigSpec &D = cemux->connections_.at(cemuxAB == \A ? \B : \A);
-       SigSpec &Q = dff->connections_.at(\Q);
+       if (!cemux && !rstmux)
+               reject;
+endcode
+
+code
        Const rst;
-       if (rstmux)
+       SigSpec D;
+       if (cemux) {
+               D = port(cemux, cemuxAB == \A ? \B : \A);
+               if (rstmux)
+                       rst = port(rstmux, rstmuxBA).as_const();
+               else
+                       rst = Const(State::Sx, GetSize(D));
+       }
+       else {
+               log_assert(rstmux);
+               D = port(rstmux, rstmuxBA  == \B ? \A : \B);
                rst = port(rstmux, rstmuxBA).as_const();
+       }
+       SigSpec Q = port(dff, \Q);
        int width = GetSize(D);
 
-       if (D[width-1] == D[width-2]) {
-               did_something = true;
+       SigSpec &dffD = dff->connections_.at(\D);
+       SigSpec &dffQ = dff->connections_.at(\Q);
+       Const init;
+       for (const auto &b : Q) {
+               auto it = b.wire->attributes.find(\init);
+               init.bits.push_back(it == b.wire->attributes.end() ? State::Sx : it->second[b.offset]);
+       }
 
-               SigBit sign = D[width-1];
-               bool is_signed = sign.wire;
-               int i;
-               for (i = width-1; i >= 2; i--) {
-                       if (!is_signed) {
-                               module->connect(Q[i], sign);
-                               if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
-                                       break;
-                       }
-                       else {
-                               module->connect(Q[i], Q[i-1]);
-                               if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
-                                       break;
-                       }
-               }
+       auto cmpx = [=](State lhs, State rhs) {
+               if (lhs == State::Sx || rhs == State::Sx)
+                       return true;
+               return lhs == rhs;
+       };
 
-               cemux->connections_.at(\A).remove(i, width-i);
-               cemux->connections_.at(\B).remove(i, width-i);
-               cemux->connections_.at(\Y).remove(i, width-i);
-               cemux->fixup_parameters();
-               dff->connections_.at(\D).remove(i, width-i);
-               dff->connections_.at(\Q).remove(i, width-i);
+       int i = width-1;
+       while (i > 1) {
+               log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]);
+               if (D[i] != D[i-1])
+                       break;
+               if (!cmpx(rst[i], rst[i-1]))
+                       break;
+               if (!cmpx(init[i], init[i-1]))
+                       break;
+               if (!cmpx(rst[i], init[i]))
+                       break;
+               module->connect(Q[i], Q[i-1]);
+               i--;
+       }
+       if (i < width-1) {
+               did_something = true;
+               if (cemux) {
+                       SigSpec &ceA = cemux->connections_.at(\A);
+                       SigSpec &ceB = cemux->connections_.at(\B);
+                       SigSpec &ceY = cemux->connections_.at(\Y);
+                       ceA.remove(i, width-1-i);
+                       ceB.remove(i, width-1-i);
+                       ceY.remove(i, width-1-i);
+                       cemux->fixup_parameters();
+               }
+               if (rstmux) {
+                       SigSpec &rstA = rstmux->connections_.at(\A);
+                       SigSpec &rstB = rstmux->connections_.at(\B);
+                       SigSpec &rstY = rstmux->connections_.at(\Y);
+                       rstA.remove(i, width-1-i);
+                       rstB.remove(i, width-1-i);
+                       rstY.remove(i, width-1-i);
+                       rstmux->fixup_parameters();
+               }
+               dffD.remove(i, width-1-i);
+               dffQ.remove(i, width-1-i);
                dff->fixup_parameters();
 
-               log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
-               accept;
+               log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux, "n/a"), log_id(rstmux, "n/a"), width-1-i);
+               width = i+1;
        }
-       else {
+       if (cemux) {
+               SigSpec &ceA = cemux->connections_.at(\A);
+               SigSpec &ceB = cemux->connections_.at(\B);
+               SigSpec &ceY = cemux->connections_.at(\Y);
+
                int count = 0;
                for (int i = width-1; i >= 0; i--) {
                        if (D[i].wire)
                                continue;
-                       Wire *w = Q[i].wire;
-                       auto it = w->attributes.find(\init);
-                       State init;
-                       if (it != w->attributes.end())
-                               init = it->second[Q[i].offset];
-                       else
-                               init = State::Sx;
-
-                       if (init == State::Sx || init == D[i].data) {
+                       if (cmpx(rst[i], D[i].data) && cmpx(init[i], D[i].data)) {
                                count++;
                                module->connect(Q[i], D[i]);
-                               cemux->connections_.at(\A).remove(i);
-                               cemux->connections_.at(\B).remove(i);
-                               cemux->connections_.at(\Y).remove(i);
-                               dff->connections_.at(\D).remove(i);
-                               dff->connections_.at(\Q).remove(i);
+                               ceA.remove(i);
+                               ceB.remove(i);
+                               ceY.remove(i);
+                               dffD.remove(i);
+                               dffQ.remove(i);
                        }
                }
                if (count > 0) {
                        did_something = true;
                        cemux->fixup_parameters();
                        dff->fixup_parameters();
-                       log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
+                       log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), log_id(rstmux, "n/a"), count);
                }
+       }
 
+       if (did_something)
                accept;
-       }
 endcode