Merge pull request #3185 from YosysHQ/micko/co_sim

[yosys.git] / passes / pmgen / xilinx_srl.cc

diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index 24b525b93e1d88ea1b0e357786a7ec30066db790..a66a06586cce23a97bc9b625a5180842d6716e72 100644 (file)
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *            (C) 2019  Eddie Hung    <eddie@fpgeh.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
@@ -48,7 +48,7 @@ void run_fixed(xilinx_srl_pm &pm)
                                initval.append(State::Sx);
                }
                else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
-                       if (cell->parameters.at(ID::INIT, State::S0).as_bool())
+                       if (cell->getParam(ID::INIT).as_bool())
                                initval.append(State::S1);
                        else
                                initval.append(State::S0);
@@ -71,7 +71,7 @@ void run_fixed(xilinx_srl_pm &pm)
                else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
                        c->setParam(ID(CLKPOL), 0);
                else if (first_cell->type.in(ID(FDRE))) {
-                       if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool())
+                       if (!first_cell->getParam(ID(IS_C_INVERTED)).as_bool())
                                c->setParam(ID(CLKPOL), 1);
                        else
                                c->setParam(ID(CLKPOL), 0);
@@ -188,7 +188,7 @@ void run_variable(xilinx_srl_pm &pm)
 
 struct XilinxSrlPass : public Pass {
        XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -212,7 +212,7 @@ struct XilinxSrlPass : public Pass {
                log("\n");
        }
 
-       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::vector<std::string> args, RTLIL::Design *design) override
        {
                log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");