/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* (C) 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-// for peepopt_pm
-bool did_something;
-
#include "passes/pmgen/xilinx_srl_pm.h"
-#include "passes/pmgen/ice40_dsp_pm.h"
-#include "passes/pmgen/peepopt_pm.h"
void run_fixed(xilinx_srl_pm &pm)
{
auto &st = pm.st_fixed;
auto &ud = pm.ud_fixed;
- auto param_def = [&ud](Cell *cell, IdString param) {
- auto def = ud.default_params.at(std::make_pair(cell->type,param));
- return cell->parameters.at(param, def);
- };
-
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
- auto first_cell = ud.longest_chain.back();
-
SigSpec initval;
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", log_id(cell));
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
- SigBit Q = cell->getPort(ID(Q));
+ SigBit Q = cell->getPort(ID::Q);
log_assert(Q.wire);
- auto it = Q.wire->attributes.find(ID(init));
+ auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset];
initval.append(i);
else
initval.append(State::Sx);
}
- else if (cell->type.in(ID(FDRE), ID(FDRE_1)))
- initval.append(param_def(cell, ID(INIT)));
+ else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
+ if (cell->getParam(ID::INIT).as_bool())
+ initval.append(State::S1);
+ else
+ initval.append(State::S0);
+ }
else
log_abort();
- if (cell != first_cell)
- pm.autoremove(cell);
+ pm.autoremove(cell);
}
+ auto first_cell = ud.longest_chain.back();
auto last_cell = ud.longest_chain.front();
Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
- c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
- c->setParam(ID(INIT), initval.as_const());
+ c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
+ c->setParam(ID::INIT, initval.as_const());
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setParam(ID(CLKPOL), 1);
- else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
+ else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
c->setParam(ID(CLKPOL), 0);
- else if (first_cell->type.in(ID(FDRE)))
- c->setParam(ID(CLKPOL), param_def(first_cell, ID(IS_C_INVERTED)).as_bool() ? 0 : 1);
+ else if (first_cell->type.in(ID(FDRE))) {
+ if (!first_cell->getParam(ID(IS_C_INVERTED)).as_bool())
+ c->setParam(ID(CLKPOL), 1);
+ else
+ c->setParam(ID(CLKPOL), 0);
+ }
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
else
c->setParam(ID(ENPOL), 2);
- c->setPort(ID(C), first_cell->getPort(ID(C)));
- c->setPort(ID(D), first_cell->getPort(ID(D)));
- c->setPort(ID(Q), last_cell->getPort(ID(Q)));
- c->setPort(ID(L), GetSize(ud.longest_chain)-1);
+ c->setPort(ID::C, first_cell->getPort(ID::C));
+ c->setPort(ID::D, first_cell->getPort(ID::D));
+ c->setPort(ID::Q, last_cell->getPort(ID::Q));
+ c->setPort(ID::L, GetSize(ud.longest_chain)-1);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
- c->setPort(ID(E), State::S1);
+ c->setPort(ID::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
- c->setPort(ID(E), first_cell->getPort(ID(E)));
+ c->setPort(ID::E, first_cell->getPort(ID::E));
else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
- c->setPort(ID(E), first_cell->getPort(ID(CE)));
+ c->setPort(ID::E, first_cell->getPort(ID(CE)));
else
log_abort();
}
log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
- auto first_cell = ud.chain.back().first;
- auto first_slice = ud.chain.back().second;
-
SigSpec initval;
for (const auto &i : ud.chain) {
auto cell = i.first;
auto slice = i.second;
log_debug(" %s\n", log_id(cell));
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
- SigBit Q = cell->getPort(ID(Q))[slice];
+ SigBit Q = cell->getPort(ID::Q)[slice];
log_assert(Q.wire);
- auto it = Q.wire->attributes.find(ID(init));
+ auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset];
initval.append(i);
}
else
log_abort();
- if (cell != first_cell)
- cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID);
}
pm.autoremove(st.shiftx);
+ auto first_cell = ud.chain.back().first;
+ auto first_slice = ud.chain.back().second;
+
Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
- c->setParam(ID(DEPTH), GetSize(ud.chain));
- c->setParam(ID(INIT), initval.as_const());
+ c->setParam(ID::DEPTH, GetSize(ud.chain));
+ c->setParam(ID::INIT, initval.as_const());
Const clkpol, enpol;
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
clkpol = 1;
- else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_)))
+ else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
clkpol = 0;
else if (first_cell->type.in(ID($dff), ID($dffe)))
- clkpol = first_cell->getParam(ID(CLK_POLARITY));
+ clkpol = first_cell->getParam(ID::CLK_POLARITY);
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
enpol = 0;
else if (first_cell->type.in(ID($dffe)))
- enpol = first_cell->getParam(ID(EN_POLARITY));
+ enpol = first_cell->getParam(ID::EN_POLARITY);
else
enpol = 2;
c->setParam(ID(CLKPOL), clkpol);
c->setParam(ID(ENPOL), enpol);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
- c->setPort(ID(C), first_cell->getPort(ID(C)));
+ c->setPort(ID::C, first_cell->getPort(ID::C));
else if (first_cell->type.in(ID($dff), ID($dffe)))
- c->setPort(ID(C), first_cell->getPort(ID(CLK)));
+ c->setPort(ID::C, first_cell->getPort(ID::CLK));
else
log_abort();
- c->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]);
- c->setPort(ID(Q), st.shiftx->getPort(ID(Y)));
- c->setPort(ID(L), st.shiftx->getPort(ID(B)));
+ c->setPort(ID::D, first_cell->getPort(ID::D)[first_slice]);
+ c->setPort(ID::Q, st.shiftx->getPort(ID::Y));
+ c->setPort(ID::L, st.shiftx->getPort(ID::B));
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
- c->setPort(ID(E), State::S1);
+ c->setPort(ID::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
- c->setPort(ID(E), first_cell->getPort(ID(E)));
+ c->setPort(ID::E, first_cell->getPort(ID::E));
else if (first_cell->type.in(ID($dffe)))
- c->setPort(ID(E), first_cell->getPort(ID(EN)));
+ c->setPort(ID::E, first_cell->getPort(ID::EN));
else
log_abort();
}
struct XilinxSrlPass : public Pass {
XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log("\n");
log(" -variable\n");
log(" infer variable-length shift registers (i.e. fixed-length shifts where\n");
- log(" each element also fans-out to a $shiftx cell.\n");
+ log(" each element also fans-out to a $shiftx cell).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
pm.ud_fixed.minlen = minlen;
pm.ud_variable.minlen = minlen;
- if (fixed) {
- // TODO: How to get these automatically?
- pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0;
- pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0;
- pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0;
- pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
+ if (fixed)
pm.run_fixed(run_fixed);
- }
if (variable)
pm.run_variable(run_variable);
}
projects / yosys.git / blobdiff