Renamed extend() to extend_xx(), changed most users to extend_u0()

[yosys.git] / passes / proc / proc_arst.cc

diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 676469fe2dbf669f65d503894e407449c3b903ab..0874d0981ae6e0b383afd918052c772be08e007c 100644 (file)
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -23,10 +23,14 @@
 #include <stdlib.h>
 #include <stdio.h>
 
-// defined in proc_clean.cc
+YOSYS_NAMESPACE_BEGIN
 extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth);
+YOSYS_NAMESPACE_END
 
-static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity)
 {
        if (signal.size() != 1)
                return false;
@@ -35,45 +39,45 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
 
        for (auto cell : mod->cells())
        {
-               if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
-                       return check_signal(mod, cell->get("\\A"), ref, polarity);
+               if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal)
+                       return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 
-               if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
-                       return check_signal(mod, cell->get("\\A"), ref, polarity);
+               if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal)
+                       return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 
-               if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
+               if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) {
                        polarity = !polarity;
-                       return check_signal(mod, cell->get("\\A"), ref, polarity);
+                       return check_signal(mod, cell->getPort("\\A"), ref, polarity);
                }
 
-               if (cell->type == "$not" && cell->get("\\Y") == signal) {
+               if (cell->type == "$not" && cell->getPort("\\Y") == signal) {
                        polarity = !polarity;
-                       return check_signal(mod, cell->get("\\A"), ref, polarity);
+                       return check_signal(mod, cell->getPort("\\A"), ref, polarity);
                }
 
-               if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
-                       if (cell->get("\\A").is_fully_const()) {
-                               if (!cell->get("\\A").as_bool())
+               if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) {
+                       if (cell->getPort("\\A").is_fully_const()) {
+                               if (!cell->getPort("\\A").as_bool())
                                        polarity = !polarity;
-                               return check_signal(mod, cell->get("\\B"), ref, polarity);
+                               return check_signal(mod, cell->getPort("\\B"), ref, polarity);
                        }
-                       if (cell->get("\\B").is_fully_const()) {
-                               if (!cell->get("\\B").as_bool())
+                       if (cell->getPort("\\B").is_fully_const()) {
+                               if (!cell->getPort("\\B").as_bool())
                                        polarity = !polarity;
-                               return check_signal(mod, cell->get("\\A"), ref, polarity);
+                               return check_signal(mod, cell->getPort("\\A"), ref, polarity);
                        }
                }
 
-               if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
-                       if (cell->get("\\A").is_fully_const()) {
-                               if (cell->get("\\A").as_bool())
+               if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) {
+                       if (cell->getPort("\\A").is_fully_const()) {
+                               if (cell->getPort("\\A").as_bool())
                                        polarity = !polarity;
-                               return check_signal(mod, cell->get("\\B"), ref, polarity);
+                               return check_signal(mod, cell->getPort("\\B"), ref, polarity);
                        }
-                       if (cell->get("\\B").is_fully_const()) {
-                               if (cell->get("\\B").as_bool())
+                       if (cell->getPort("\\B").is_fully_const()) {
+                               if (cell->getPort("\\B").as_bool())
                                        polarity = !polarity;
-                               return check_signal(mod, cell->get("\\A"), ref, polarity);
+                               return check_signal(mod, cell->getPort("\\A"), ref, polarity);
                        }
                }
        }
@@ -81,7 +85,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
        return false;
 }
 
-static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::SigSpec &rval, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity, bool unknown)
+void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::SigSpec &rval, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity, bool unknown)
 {
        for (auto &action : cs->actions) {
                if (unknown)
@@ -114,7 +118,7 @@ static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::S
        }
 }
 
-static void eliminate_const(RTLIL::Module *mod, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity)
+void eliminate_const(RTLIL::Module *mod, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity)
 {
        for (auto sw : cs->switches) {
                bool this_polarity = polarity;
@@ -149,7 +153,7 @@ static void eliminate_const(RTLIL::Module *mod, RTLIL::CaseRule *cs, RTLIL::SigS
        }
 }
 
-static void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
+void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
 {
 restart_proc_arst:
        if (proc->root_case.switches.size() != 1)
@@ -170,7 +174,7 @@ restart_proc_arst:
                                for (auto &action : sync->actions) {
                                        RTLIL::SigSpec rspec = action.second;
                                        RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size());
-                                       for (int i = 0; i < SIZE(rspec); i++)
+                                       for (int i = 0; i < GetSize(rspec); i++)
                                                if (rspec[i].wire == NULL)
                                                        rval[i] = rspec[i];
                                        RTLIL::SigSpec last_rval;
@@ -258,7 +262,7 @@ struct ProcArstPass : public Pass {
                                                                for (auto &chunk : act.first.chunks())
                                                                        if (chunk.wire && chunk.wire->attributes.count("\\init")) {
                                                                                RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
-                                                                               value.extend(chunk.wire->width, false);
+                                                                               value.extend_xx(chunk.wire->width, false);
                                                                                arst_sig.append(chunk);
                                                                                arst_val.append(value.extract(chunk.offset, chunk.width));
                                                                        }
@@ -280,3 +284,4 @@ struct ProcArstPass : public Pass {
        }
 } ProcArstPass;
  
+PRIVATE_NAMESPACE_END