/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
#include <stdlib.h>
#include <stdio.h>
-static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
-{
- assert(rule.compare.size() == 0);
-
- while (1) {
- sig.optimize();
- RTLIL::SigSpec tmp = sig;
- for (auto &it : rule.actions)
- tmp.replace(it.first, it.second);
- if (tmp == sig)
- break;
- sig = tmp;
- }
-}
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
-static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
+void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
{
- bool found_init = false;
-
for (auto &sync : proc->syncs)
if (sync->type == RTLIL::SyncType::STi)
{
- found_init = true;
log("Found init rule in `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
for (auto &action : sync->actions)
{
RTLIL::SigSpec lhs = action.first;
- RTLIL::SigSpec rhs = action.second;
-
- lhs.optimize();
- proc_get_const(rhs, proc->root_case);
+ RTLIL::SigSpec rhs = sigmap(action.second);
if (!rhs.is_fully_const())
log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
int offset = 0;
- for (size_t i = 0; i < lhs.chunks().size(); i++) {
- if (lhs.chunks()[i].wire == NULL)
- continue;
- RTLIL::Wire *wire = lhs.chunks()[i].wire;
- RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width);
- if (value.size() != wire->width)
- log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value));
- log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value));
- wire->attributes["\\init"] = value.as_const();
- offset += wire->width;
+ for (auto &lhs_c : lhs.chunks())
+ {
+ if (lhs_c.wire != nullptr)
+ {
+ SigSpec valuesig = rhs.extract(offset, lhs_c.width);
+ if (!valuesig.is_fully_const())
+ log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
+
+ Const value = valuesig.as_const();
+ Const &wireinit = lhs_c.wire->attributes[ID::init];
+
+ while (GetSize(wireinit.bits) < lhs_c.wire->width)
+ wireinit.bits.push_back(State::Sx);
+
+ for (int i = 0; i < lhs_c.width; i++) {
+ auto &initbit = wireinit.bits[i + lhs_c.offset];
+ if (initbit != State::Sx && initbit != value[i])
+ log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
+ initbit = value[i];
+ }
+
+ log(" Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
+ }
+ offset += lhs_c.width;
}
}
+ sync->actions.clear();
}
-
- if (found_init) {
- std::vector<RTLIL::SyncRule*> new_syncs;
- for (auto &sync : proc->syncs)
- if (sync->type == RTLIL::SyncType::STi)
- delete sync;
- else
- new_syncs.push_back(sync);
- proc->syncs.swap(new_syncs);
- }
}
struct ProcInitPass : public Pass {
ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { }
- virtual void help()
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" proc_init [selection]\n");
log("\n");
- log("This pass extracts the 'init' actions from processes (generated from verilog\n");
+ log("This pass extracts the 'init' actions from processes (generated from Verilog\n");
log("'initial' blocks) and sets the initial value to the 'init' attribute on the\n");
log("respective wire.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
- log_header("Executing PROC_INIT pass (extract init attributes).\n");
+ log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
- if (design->selected(mod_it.second))
- for (auto &proc_it : mod_it.second->processes)
- if (design->selected(mod_it.second, proc_it.second))
- proc_init(mod_it.second, proc_it.second);
+ for (auto mod : design->modules())
+ if (design->selected(mod)) {
+ SigMap sigmap(mod);
+ for (auto &proc_it : mod->processes)
+ if (design->selected(mod, proc_it.second))
+ proc_init(mod, sigmap, proc_it.second);
+ }
}
} ProcInitPass;
-
+
+PRIVATE_NAMESPACE_END
projects / yosys.git / blobdiff