dfflegalize: Add tests for aldff lowering.

[yosys.git] / passes / proc / proc_init.cc

diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index dc00019aadbea0d76460e9660226c0a9727855b2..4da20c3953959cd9f92be6327e84c9d8973e9cd5 100644 (file)
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -28,12 +28,9 @@ PRIVATE_NAMESPACE_BEGIN
 
 void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
 {
-       bool found_init = false;
-
        for (auto &sync : proc->syncs)
                if (sync->type == RTLIL::SyncType::STi)
                {
-                       found_init = true;
                        log("Found init rule in `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
 
                        for (auto &action : sync->actions)
@@ -71,22 +68,13 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
                                        offset += lhs_c.width;
                                }
                        }
+                       sync->actions.clear();
                }
-
-       if (found_init) {
-               std::vector<RTLIL::SyncRule*> new_syncs;
-               for (auto &sync : proc->syncs)
-                       if (sync->type == RTLIL::SyncType::STi)
-                               delete sync;
-                       else
-                               new_syncs.push_back(sync);
-               proc->syncs.swap(new_syncs);
-       }
 }
 
 struct ProcInitPass : public Pass {
        ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { }
-       void help() YS_OVERRIDE
+       void help() override
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -97,7 +85,7 @@ struct ProcInitPass : public Pass {
                log("respective wire.\n");
                log("\n");
        }
-       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       void execute(std::vector<std::string> args, RTLIL::Design *design) override
        {
                log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");