Merge pull request #3 from YosysHQ/master

[yosys.git] / passes / proc / proc_init.cc

diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 0c8fb83dc1fd81784613c8c68c42ec3233c1c57f..e2dc07e5356ce3c5582411f6050621c5f92d03fe 100644 (file)
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -102,7 +102,7 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
 
 struct ProcInitPass : public Pass {
        ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { }
-       virtual void help()
+       void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -113,7 +113,7 @@ struct ProcInitPass : public Pass {
                log("respective wire.\n");
                log("\n");
        }
-       virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
                log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");