Merge pull request #3 from YosysHQ/master

[yosys.git] / passes / proc / proc_init.cc

diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 633d4e58ad4a790366f53ecc36fed402719d6ec2..e2dc07e5356ce3c5582411f6050621c5f92d03fe 100644 (file)
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -61,13 +61,28 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
                                        log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
 
                                int offset = 0;
-                               for (auto &lhs_c : lhs.chunks()) {
-                                       if (lhs_c.wire != NULL) {
-                                               RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
-                                               if (value.size() != lhs_c.wire->width)
-                                                       log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
-                                               log("  Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
-                                               lhs_c.wire->attributes["\\init"] = value.as_const();
+                               for (auto &lhs_c : lhs.chunks())
+                               {
+                                       if (lhs_c.wire != nullptr)
+                                       {
+                                               SigSpec valuesig = rhs.extract(offset, lhs_c.width);
+                                               if (!valuesig.is_fully_const())
+                                                       log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
+
+                                               Const value = valuesig.as_const();
+                                               Const &wireinit = lhs_c.wire->attributes["\\init"];
+
+                                               while (GetSize(wireinit.bits) < lhs_c.wire->width)
+                                                       wireinit.bits.push_back(State::Sx);
+
+                                               for (int i = 0; i < lhs_c.width; i++) {
+                                                       auto &initbit = wireinit.bits[i + lhs_c.offset];
+                                                       if (initbit != State::Sx && initbit != value[i])
+                                                               log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
+                                                       initbit = value[i];
+                                               }
+
+                                               log("  Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
                                        }
                                        offset += lhs_c.width;
                                }
@@ -87,7 +102,7 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
 
 struct ProcInitPass : public Pass {
        ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { }
-       virtual void help()
+       void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
@@ -98,9 +113,9 @@ struct ProcInitPass : public Pass {
                log("respective wire.\n");
                log("\n");
        }
-       virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
-               log_header("Executing PROC_INIT pass (extract init attributes).\n");
+               log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
 
                extra_args(args, 1, design);