Error out if no top module given before 'sim'

[yosys.git] / passes / sat / sim.cc

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index fadffcdbc3f82d7f3b0f11ca5613e7cf999547cc..4c3022c709d451d7a48d5f63800209025fb178ac 100644 (file)
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -88,6 +88,8 @@ struct SimInstance
        SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
                        shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
        {
+               log_assert(module);
+
                if (parent) {
                        log_assert(parent->children.count(instance) == 0);
                        parent->children[instance] = this;
@@ -778,7 +780,7 @@ struct SimPass : public Pass {
                log("        number of cycles to simulate (default: 20)\n");
                log("\n");
                log("    -a\n");
-               log("        include all nets in VCD output, nut just those with public names\n");
+               log("        include all nets in VCD output, not just those with public names\n");
                log("\n");
                log("    -w\n");
                log("        writeback mode: use final simulation state as new init state\n");
@@ -848,6 +850,9 @@ struct SimPass : public Pass {
 
                if (design->full_selection()) {
                        top_mod = design->top_module();
+
+                       if (!top_mod)
+                               log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
                } else {
                        auto mods = design->selected_whole_modules();
                        if (GetSize(mods) != 1)