Proper SigBit forming in sim

[yosys.git] / passes / sat / sim.cc

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index f225ebd158218e904dd820a8bec5fb86a36f01e6..b56ccb987e01d7d4f413a4199a5aa5af0fb0053b 100644 (file)
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1138,13 +1138,13 @@ struct SimWorker : SimShared
                        if (index < w->start_offset || index > w->start_offset + w->width)
                                log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
                        if (type == "input") {
-                               inputs[variable] = {SigBit(w,index), false};
+                               inputs[variable] = {SigBit(w,index-w->start_offset), false};
                        } else if (type == "init") {
-                               inits[variable] = {SigBit(w,index), false};
+                               inits[variable] = {SigBit(w,index-w->start_offset), false};
                        } else if (type == "latch") {
-                               latches[variable] = {SigBit(w,index), false};
+                               latches[variable] = {SigBit(w,index-w->start_offset), false};
                        } else if (type == "invlatch") {
-                               latches[variable] = {SigBit(w,index), true};
+                               latches[variable] = {SigBit(w,index-w->start_offset), true};
                        }
                }