bool clk_polarity, en_polarity;
RTLIL::SigSpec clk_sig, en_sig;
-inline std::string remap_name(RTLIL::IdString abc_name)
+inline std::string remap_name(RTLIL::IdString abc9_name)
{
- return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
+ return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
}
-void handle_loops(RTLIL::Design *design,
- const dict<IdString,pool<IdString>> &scc_break_inputs)
+void handle_loops(RTLIL::Design *design)
{
- Pass::call(design, "scc -set_attr abc_scc_id {}");
+ Pass::call(design, "scc -set_attr abc9_scc_id {}");
// For every unique SCC found, (arbitrarily) find the first
// cell in the component, and select (and mark) all its output
// wires
pool<RTLIL::Const> ids_seen;
- for (auto cell : module->selected_cells()) {
- auto it = cell->attributes.find(ID(abc_scc_id));
+ for (auto cell : module->cells()) {
+ auto it = cell->attributes.find(ID(abc9_scc_id));
if (it != cell->attributes.end()) {
auto r = ids_seen.insert(it->second);
if (r.second) {
log_assert(w->port_input);
log_assert(b.offset < GetSize(w));
}
- w->set_bool_attribute(ID(abc_scc_break));
+ w->set_bool_attribute(ID(abc9_scc_break));
module->swap_names(b.wire, w);
c.second = RTLIL::SigBit(w, b.offset);
}
}
cell->attributes.erase(it);
}
-
- auto jt = scc_break_inputs.find(cell->type);
- if (jt != scc_break_inputs.end())
- for (auto port_name : jt->second) {
- RTLIL::SigSpec sig;
- auto &rhs = cell->connections_.at(port_name);
- for (auto b : rhs) {
- Wire *w = b.wire;
- if (!w) continue;
- w->port_output = true;
- w->set_bool_attribute(ID(abc_scc_break));
- w = module->wire(stringf("%s.abci", w->name.c_str()));
- if (!w) {
- w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
- w->port_input = true;
- }
- else {
- log_assert(b.offset < GetSize(w));
- log_assert(w->port_input);
- }
- sig.append(RTLIL::SigBit(w, b.offset));
- }
- rhs = sig;
- }
}
module->fixup_ports();
}
-std::string add_echos_to_abc_cmd(std::string str)
+std::string add_echos_to_abc9_cmd(std::string str)
{
std::string new_str, token;
for (size_t i = 0; i < str.size(); i++) {
return new_str;
}
-std::string fold_abc_cmd(std::string str)
+std::string fold_abc9_cmd(std::string str)
{
std::string token, new_str = " ";
int char_counter = 10;
return text;
}
-struct abc_output_filter
+struct abc9_output_filter
{
bool got_cr;
int escape_seq_state;
std::string tempdir_name;
bool show_tempdir;
- abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
+ abc9_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
{
got_cr = false;
escape_seq_state = 0;
};
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
- bool cleanup, vector<int> lut_costs, bool /*retime_mode*/, std::string clk_str,
+ bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
bool show_tempdir, std::string box_file, std::string lut_file,
- std::string wire_delay, const dict<int,IdString> &box_lookup,
- const dict<IdString,pool<IdString>> &scc_break_inputs
+ std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs
)
{
module = current_module;
clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
}
- //if (retime_mode && clk_sig.empty())
- // log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
+ if (dff_mode && clk_sig.empty())
+ log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
if (!cleanup)
log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
- std::string abc_script;
+ std::string abc9_script;
if (!lut_costs.empty()) {
- abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
+ abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
if (!box_file.empty())
- abc_script += stringf("read_box -v %s; ", box_file.c_str());
+ abc9_script += stringf("read_box -v %s; ", box_file.c_str());
}
else
if (!lut_file.empty()) {
- abc_script += stringf("read_lut %s; ", lut_file.c_str());
+ abc9_script += stringf("read_lut %s; ", lut_file.c_str());
if (!box_file.empty())
- abc_script += stringf("read_box -v %s; ", box_file.c_str());
+ abc9_script += stringf("read_box -v %s; ", box_file.c_str());
}
else
log_abort();
- abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
+ abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
if (!script_file.empty()) {
if (script_file[0] == '+') {
for (size_t i = 1; i < script_file.size(); i++)
if (script_file[i] == '\'')
- abc_script += "'\\''";
+ abc9_script += "'\\''";
else if (script_file[i] == ',')
- abc_script += " ";
+ abc9_script += " ";
else
- abc_script += script_file[i];
+ abc9_script += script_file[i];
} else
- abc_script += stringf("source %s", script_file.c_str());
+ abc9_script += stringf("source %s", script_file.c_str());
} else if (!lut_costs.empty() || !lut_file.empty()) {
//bool all_luts_cost_same = true;
//for (int this_cost : lut_costs)
// if (this_cost != lut_costs.front())
// all_luts_cost_same = false;
- abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
+ abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
//if (all_luts_cost_same && !fast_mode)
- // abc_script += "; lutpack {S}";
+ // abc9_script += "; lutpack {S}";
} else
log_abort();
//if (script_file.empty() && !delay_target.empty())
- // for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
- // abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
+ // for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1))
+ // abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8);
- for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
- abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
+ for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos))
+ abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3);
- //for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
- // abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
+ //for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
+ // abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
- for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos))
- abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3);
+ for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
+ abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
- abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
- abc_script = add_echos_to_abc_cmd(abc_script);
+ if (nomfs)
+ for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
+ abc9_script = abc9_script.erase(pos, strlen("&mfs"));
- for (size_t i = 0; i+1 < abc_script.size(); i++)
- if (abc_script[i] == ';' && abc_script[i+1] == ' ')
- abc_script[i+1] = '\n';
+ abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
+ abc9_script = add_echos_to_abc9_cmd(abc9_script);
+
+ for (size_t i = 0; i+1 < abc9_script.size(); i++)
+ if (abc9_script[i] == ';' && abc9_script[i+1] == ' ')
+ abc9_script[i+1] = '\n';
FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
- fprintf(f, "%s\n", abc_script.c_str());
+ fprintf(f, "%s\n", abc9_script.c_str());
fclose(f);
- if (/*retime_mode ||*/ !clk_str.empty())
+ if (dff_mode || !clk_str.empty())
{
if (clk_sig.size() == 0)
log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
- handle_loops(design, scc_break_inputs);
+ handle_loops(design);
Pass::call(design, "aigmap");
//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
// count_gates, GetSize(signal_list), count_input, count_output);
-#if 0
- Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.v", tempdir_name.c_str()));
-#endif
Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
std::string buffer;
// the expose operation -- remove them from PO/PI
// and re-connecting them back together
for (auto wire : module->wires()) {
- auto it = wire->attributes.find(ID(abc_scc_break));
+ auto it = wire->attributes.find(ID(abc9_scc_break));
if (it != wire->attributes.end()) {
wire->attributes.erase(it);
log_assert(wire->port_output);
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
#ifndef YOSYS_LINK_ABC
- abc_output_filter filt(tempdir_name, show_tempdir);
- int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
+ abc9_output_filter filt(tempdir_name, show_tempdir);
+ int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1));
#else
// These needs to be mutable, supposedly due to getopt
- char *abc_argv[5];
+ char *abc9_argv[5];
string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
- abc_argv[0] = strdup(exe_file.c_str());
- abc_argv[1] = strdup("-s");
- abc_argv[2] = strdup("-f");
- abc_argv[3] = strdup(tmp_script_name.c_str());
- abc_argv[4] = 0;
- int ret = Abc_RealMain(4, abc_argv);
- free(abc_argv[0]);
- free(abc_argv[1]);
- free(abc_argv[2]);
- free(abc_argv[3]);
+ abc9_argv[0] = strdup(exe_file.c_str());
+ abc9_argv[1] = strdup("-s");
+ abc9_argv[2] = strdup("-f");
+ abc9_argv[3] = strdup(tmp_script_name.c_str());
+ abc9_argv[4] = 0;
+ int ret = Abc_RealMain(4, abc9_argv);
+ free(abc9_argv[0]);
+ free(abc9_argv[1]);
+ free(abc9_argv[2]);
+ free(abc9_argv[3]);
#endif
if (ret != 0)
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
- ifs.open(buffer);
+ ifs.open(buffer, std::ifstream::binary);
if (ifs.fail())
log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
for (int i = 0; i < GetSize(w); i++)
output_bits.insert({wire, i});
}
-
- auto jt = w->attributes.find("\\init");
- if (jt != w->attributes.end()) {
- auto r = remap_wire->attributes.insert(std::make_pair("\\init", jt->second));
- log_assert(r.second);
- }
}
for (auto &it : module->connections_) {
signal = std::move(bits);
}
- dict<IdString, bool> abc_box;
+ dict<IdString, bool> abc9_box;
vector<RTLIL::Cell*> boxes;
- for (auto cell : module->selected_cells()) {
- if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC_FF_))) {
+ for (const auto &it : module->cells_) {
+ auto cell = it.second;
+ if (cell->type.in(ID($_AND_), ID($_NOT_))) {
module->remove(cell);
continue;
}
- auto jt = abc_box.find(cell->type);
- if (jt == abc_box.end()) {
+ auto jt = abc9_box.find(cell->type);
+ if (jt == abc9_box.end()) {
RTLIL::Module* box_module = design->module(cell->type);
- jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc_box_id)))).first;
+ jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
}
if (jt->second)
boxes.emplace_back(cell);
dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
std::map<IdString, int> cell_stats;
- for (auto mapped_cell : mapped_mod->cells())
+ for (auto c : mapped_mod->cells())
{
- toposort.node(mapped_cell->name);
+ toposort.node(c->name);
RTLIL::Cell *cell = nullptr;
- if (mapped_cell->type == ID($_NOT_)) {
- RTLIL::SigBit a_bit = mapped_cell->getPort(ID(A));
- RTLIL::SigBit y_bit = mapped_cell->getPort(ID(Y));
+ if (c->type == ID($_NOT_)) {
+ RTLIL::SigBit a_bit = c->getPort(ID::A);
+ RTLIL::SigBit y_bit = c->getPort(ID::Y);
+ bit_users[a_bit].insert(c->name);
+ bit_drivers[y_bit].insert(c->name);
if (!a_bit.wire) {
- mapped_cell->setPort(ID(Y), module->addWire(NEW_ID));
+ c->setPort(ID::Y, module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
}
- else {
- RTLIL::Cell* driving_lut = nullptr;
+ else if (!lut_costs.empty() || !lut_file.empty()) {
+ RTLIL::Cell* driver_lut = nullptr;
// ABC can return NOT gates that drive POs
if (!a_bit.wire->port_input) {
// If it's not a NOT gate that that comes from a PI directly,
driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
else
driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
- driving_lut = mapped_mod->cell(driver_name);
+ driver_lut = mapped_mod->cell(driver_name);
}
- if (!driving_lut) {
+ if (!driver_lut) {
// If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT
- cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
+ cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
- bit2sinks[cell->getPort(ID(A))].push_back(cell);
+ bit2sinks[cell->getPort(ID::A)].push_back(cell);
cell_stats[ID($lut)]++;
- bit_users[a_bit].insert(mapped_cell->name);
- bit_drivers[y_bit].insert(mapped_cell->name);
}
else
- not2drivers[mapped_cell] = driving_lut;
+ not2drivers[c] = driver_lut;
continue;
}
+ else
+ log_abort();
if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
continue;
}
- cell_stats[mapped_cell->type]++;
+ cell_stats[c->type]++;
RTLIL::Cell *existing_cell = nullptr;
- if (mapped_cell->type == ID($lut)) {
- if (GetSize(mapped_cell->getPort(ID(A))) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
- SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID(A)).as_wire()->name));
- SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID(Y)).as_wire()->name));
+ if (c->type == ID($lut)) {
+ if (GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
+ SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID::A).as_wire()->name));
+ SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID::Y).as_wire()->name));
module->connect(my_y, my_a);
- if (markgroups) mapped_cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx;
log_abort();
continue;
}
- cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
+ cell = module->addCell(remap_name(c->name), c->type);
}
else {
- existing_cell = module->cell(mapped_cell->name);
+ existing_cell = module->cell(c->name);
log_assert(existing_cell);
- cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
- module->swap_names(cell, existing_cell);
+ cell = module->addCell(remap_name(c->name), c->type);
}
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (existing_cell) {
cell->parameters = existing_cell->parameters;
cell->attributes = existing_cell->attributes;
-
- cell->attributes.erase("\\abc_flop_clk_pol");
- cell->attributes.erase("\\abc_flop_en_pol");
}
else {
- cell->parameters = mapped_cell->parameters;
- cell->attributes = mapped_cell->attributes;
+ cell->parameters = c->parameters;
+ cell->attributes = c->attributes;
}
-
- auto abc_flop = mapped_cell->attributes.count("\\abc_flop");
- for (auto &conn : mapped_cell->connections()) {
+ for (auto &conn : c->connections()) {
RTLIL::SigSpec newsig;
for (auto c : conn.second.chunks()) {
if (c.width == 0)
}
cell->setPort(conn.first, newsig);
- if (!abc_flop) {
- if (cell->input(conn.first)) {
- for (auto i : newsig)
- bit2sinks[i].push_back(cell);
- for (auto i : conn.second)
- bit_users[i].insert(mapped_cell->name);
- }
- if (cell->output(conn.first))
- for (auto i : conn.second)
- bit_drivers[i].insert(mapped_cell->name);
+ if (cell->input(conn.first)) {
+ for (auto i : newsig)
+ bit2sinks[i].push_back(cell);
+ for (auto i : conn.second)
+ bit_users[i].insert(c->name);
}
+ if (cell->output(conn.first))
+ for (auto i : conn.second)
+ bit_drivers[i].insert(c->name);
}
}
- for (auto cell : boxes)
- module->remove(cell);
+ for (auto existing_cell : boxes) {
+ Cell *cell = module->cell(remap_name(existing_cell->name));
+ if (cell) {
+ for (auto &conn : existing_cell->connections()) {
+ if (!conn.second.is_wire())
+ continue;
+ Wire *wire = conn.second.as_wire();
+ if (!wire->get_bool_attribute(ID(abc9_padding)))
+ continue;
+ cell->unsetPort(conn.first);
+ log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second));
+ }
+ module->swap_names(cell, existing_cell);
+ }
+ module->remove(existing_cell);
+ }
// Copy connections (and rename) from mapped_mod to module
for (auto conn : mapped_mod->connections()) {
}
for (auto &it : cell_stats)
- log("ABC RESULTS: %15s cells: %8d\n", log_id(it.first), it.second);
+ log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
int in_wires = 0, out_wires = 0;
// Stitch in mapped_mod's inputs/outputs into module
- for (auto port_name : mapped_mod->ports) {
- RTLIL::Wire *port = mapped_mod->wire(port_name);
- log_assert(port);
- RTLIL::Wire *wire = module->wire(port->name);
+ for (auto port : mapped_mod->ports) {
+ RTLIL::Wire *w = mapped_mod->wire(port);
+ RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
- RTLIL::Wire *remap_wire = module->wire(remap_name(port->name));
+ RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire));
RTLIL::SigSig conn;
- if (port->port_input) {
- conn.first = remap_wire;
- conn.second = signal;
- in_wires++;
- module->connect(conn);
- }
- if (port->port_output) {
+ if (w->port_output) {
conn.first = signal;
conn.second = remap_wire;
out_wires++;
module->connect(conn);
}
+ else if (w->port_input) {
+ conn.first = remap_wire;
+ conn.second = signal;
+ in_wires++;
+ module->connect(conn);
+ }
}
for (auto &it : bit_users)
for (auto driver_cell : bit_drivers.at(it.first))
for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell);
-#if 0
- toposort.analyze_loops = true;
-#endif
- bool no_loops = toposort.sort();
-#if 0
- unsigned i = 0;
- for (auto &it : toposort.loops) {
- log(" loop %d\n", i++);
- for (auto cell_name : it) {
- auto cell = mapped_mod->cell(cell_name);
- log_assert(cell);
- log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
- }
- }
-#endif
+ bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
log_assert(no_loops);
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
if (it == not2drivers.end())
continue;
RTLIL::Cell *driver_lut = it->second;
- RTLIL::SigBit a_bit = not_cell->getPort(ID(A));
- RTLIL::SigBit y_bit = not_cell->getPort(ID(Y));
+ RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
+ RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
RTLIL::Const driver_mask;
a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
// Push downstream LUTs past inverter
for (auto sink_cell : jt->second) {
- SigSpec A = sink_cell->getPort(ID(A));
+ SigSpec A = sink_cell->getPort(ID::A);
RTLIL::Const mask = sink_cell->getParam(ID(LUT));
int index = 0;
for (; index < GetSize(A); index++)
i += 1 << (index+1);
}
A[index] = y_bit;
- sink_cell->setPort(ID(A), A);
+ sink_cell->setPort(ID::A, A);
sink_cell->setParam(ID(LUT), mask);
}
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
auto cell = module->addLut(NEW_ID,
- driver_lut->getPort(ID(A)),
+ driver_lut->getPort(ID::A),
y_bit,
driver_mask);
- for (auto &bit : cell->connections_.at(ID(A))) {
+ for (auto &bit : cell->connections_.at(ID::A)) {
bit.wire = module->wires_.at(remap_name(bit.wire->name));
bit2sinks[bit].push_back(cell);
}
log(" if no -script parameter is given, the following scripts are used:\n");
log("\n");
log(" for -lut/-luts (only one LUT size):\n");
- log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
+ log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
log("\n");
log(" for -lut/-luts (different LUT sizes):\n");
- log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
+ log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
log("\n");
log(" -fast\n");
log(" use different default scripts that are slightly faster (at the cost\n");
log(" of output quality):\n");
log("\n");
log(" for -lut/-luts:\n");
- log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
+ log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
log("\n");
log(" -D <picoseconds>\n");
log(" set delay target. the string {D} in the default scripts above is\n");
#endif
std::string script_file, clk_str, box_file, lut_file;
std::string delay_target, lutin_shared = "-S 1", wire_delay;
- bool fast_mode = false, /*retime_mode = false,*/ keepff = false, cleanup = true;
+ bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
bool show_tempdir = false;
+ bool nomfs = false;
vector<int> lut_costs;
markgroups = false;
fast_mode = true;
continue;
}
- //if (arg == "-retime") {
- // retime_mode = true;
+ //if (arg == "-dff") {
+ // dff_mode = true;
// continue;
//}
//if (arg == "-clk" && argidx+1 < args.size()) {
// clk_str = args[++argidx];
- // retime_mode = true;
+ // dff_mode = true;
// continue;
//}
//if (arg == "-keepff") {
}
if (arg == "-box" && argidx+1 < args.size()) {
box_file = args[++argidx];
- rewrite_filename(box_file);
- if (!box_file.empty() && !is_absolute_path(box_file))
- box_file = std::string(pwd) + "/" + box_file;
continue;
}
if (arg == "-W" && argidx+1 < args.size()) {
wire_delay = "-W " + args[++argidx];
continue;
}
+ if (arg == "-nomfs") {
+ nomfs = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
- if (lut_costs.empty() && lut_file.empty())
- log_cmd_error("abc9 must be called with '-lut' or '-luts'\n");
+ // ABC expects a box file for XAIG
+ if (box_file.empty())
+ box_file = "+/dummy.box";
+
+ rewrite_filename(box_file);
+ if (!box_file.empty() && !is_absolute_path(box_file))
+ box_file = std::string(pwd) + "/" + box_file;
dict<int,IdString> box_lookup;
- dict<IdString,pool<IdString>> scc_break_inputs;
for (auto m : design->modules()) {
- auto it = m->attributes.find(ID(abc_box_id));
+ auto it = m->attributes.find(ID(abc9_box_id));
if (it == m->attributes.end())
continue;
if (m->name.begins_with("$paramod"))
auto id = it->second.as_int();
auto r = box_lookup.insert(std::make_pair(id, m->name));
if (!r.second)
- log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
+ log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
log_id(m), id, log_id(r.first->second));
log_assert(r.second);
for (auto p : m->ports) {
auto w = m->wire(p);
log_assert(w);
- if (w->port_input) {
- if (w->attributes.count(ID(abc_scc_break)))
- scc_break_inputs[m->name].insert(p);
- if (w->attributes.count(ID(abc_carry_in))) {
+ if (w->attributes.count(ID(abc9_carry))) {
+ if (w->port_input) {
if (carry_in)
- log_error("Module '%s' contains more than one 'abc_carry_in' port.\n", log_id(m));
+ log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
carry_in = w;
}
- }
- if (w->port_output) {
- if (w->attributes.count(ID(abc_carry_out))) {
+ else if (w->port_output) {
if (carry_out)
- log_error("Module '%s' contains more than one 'abc_carry_out' port.\n", log_id(m));
+ log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
carry_out = w;
}
}
}
if (carry_in || carry_out) {
if (carry_in && !carry_out)
- log_error("Module '%s' contains an 'abc_carry_in' port but no 'abc_carry_out' port.\n", log_id(m));
+ log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
if (!carry_in && carry_out)
- log_error("Module '%s' contains an 'abc_carry_out' port but no 'abc_carry_in' port.\n", log_id(m));
+ log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
// Make carry_in the last PI, and carry_out the last PO
// since ABC requires it this way
auto &ports = m->ports;
for (auto mod : design->selected_modules())
{
- if (mod->attributes.count(ID(abc_box_id)))
+ if (mod->attributes.count(ID(abc9_box_id)))
continue;
if (mod->processes.size() > 0) {
assign_map.set(mod);
- if (true || /*!dff_mode ||*/ !clk_str.empty()) {
-
- design->selection_stack.emplace_back(false);
- RTLIL::Selection& sel = design->selection_stack.back();
- sel.select(mod);
-
- abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, false, clk_str, keepff,
+ if (!dff_mode || !clk_str.empty()) {
+ abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
delay_target, lutin_shared, fast_mode, show_tempdir,
- box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
- design->selection_stack.pop_back();
+ box_file, lut_file, wire_delay, box_lookup, nomfs);
continue;
}
std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
- pool<IdString> seen_cells;
- dict<IdString, std::pair<RTLIL::IdString,RTLIL::IdString>> flop_data;
-
- for (auto cell : all_cells) {
+ for (auto cell : all_cells)
+ {
clkdomain_t key;
for (auto &conn : cell->connections())
}
}
- decltype(flop_data)::iterator it;
- if (seen_cells.insert(cell->type).second) {
- RTLIL::Module* inst_module = design->module(cell->type);
- if (!inst_module)
- continue;
-
- if (!inst_module->attributes.count("\\abc_flop"))
- continue;
-
- IdString abc_flop_clk, abc_flop_en;
- for (auto port_name : inst_module->ports) {
- auto wire = inst_module->wire(port_name);
- log_assert(wire);
- if (wire->attributes.count("\\abc_flop_clk")) {
- if (abc_flop_clk != IdString())
- log_error("More than one port has the 'abc_flop_clk' attribute set on module '%s'.\n", log_id(cell->type));
- abc_flop_clk = port_name;
- }
- if (wire->attributes.count("\\abc_flop_en")) {
- if (abc_flop_en != IdString())
- log_error("More than one port has the 'abc_flop_en' attribute set on module '%s'.\n", log_id(cell->type));
- abc_flop_en = port_name;
- }
- }
-
- if (abc_flop_clk == IdString())
- log_error("'abc_flop_clk' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
- if (abc_flop_en == IdString())
- log_error("'abc_flop_en' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
- it = flop_data.insert(std::make_pair(cell->type, std::make_pair(abc_flop_clk, abc_flop_en))).first;
- }
- else {
- it = flop_data.find(cell->type);
- if (it == flop_data.end())
- continue;
- }
-
- auto jt = cell->attributes.find("\\abc_flop_clk_pol");
- if (jt == cell->parameters.end())
- log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(cell->type));
- bool this_clk_pol;
- if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
- auto param = jt->second.decode_string();
- auto kt = cell->parameters.find(param);
- if (kt == cell->parameters.end())
- log_error("'abc_flop_clk_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type));
- this_clk_pol = kt->second.as_bool();
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+ {
+ key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
}
else
- this_clk_pol = jt->second.as_bool();
- jt = cell->parameters.find("\\$abc_flop_en_pol");
- if (jt == cell->parameters.end())
- log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(cell->type));
- bool this_en_pol;
- if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
- auto param = jt->second.decode_string();
- auto kt = cell->parameters.find(param);
- if (kt == cell->parameters.end())
- log_error("'abc_flop_en_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type));
- this_en_pol = kt->second.as_bool();
+ if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ {
+ bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
+ bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
+ key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E))));
}
else
- this_en_pol = jt->second.as_bool();
-
- const auto &data = it->second;
- key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.first)), this_en_pol, assign_map(cell->getPort(data.second)));
+ continue;
unassigned_cells.erase(cell);
expand_queue.insert(cell);
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
- design->selection_stack.emplace_back(false);
- RTLIL::Selection& sel = design->selection_stack.back();
-
for (auto &it : assigned_cells) {
clk_polarity = std::get<0>(it.first);
clk_sig = assign_map(std::get<1>(it.first));
en_polarity = std::get<2>(it.first);
en_sig = assign_map(std::get<3>(it.first));
-
- pool<RTLIL::IdString> assigned_names;
- for (auto i : it.second)
- assigned_names.insert(i->name);
- sel.selected_members[mod->name] = std::move(assigned_names);
-
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
- box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
+ box_file, lut_file, wire_delay, box_lookup, nomfs);
assign_map.set(mod);
}
-
- design->selection_stack.pop_back();
}
assign_map.clear();
- // The "clean" pass also contains a design->check() call
- Pass::call(design, "clean");
-
log_pop();
}
} Abc9Pass;
projects / yosys.git / blobdiff