Output has priority over input when stitching in abc9

[yosys.git] / passes / techmap / abc9.cc

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3768786d42d929a13aa0311eb5a4bd6b5e04fe86..6fdf987f0b4529077bdcad20718b926d7a25b068 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -568,13 +568,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
                        RTLIL::Cell *cell = nullptr;
                        if (c->type == ID($_NOT_)) {
-                               RTLIL::SigBit a_bit = c->getPort(ID(A));
-                               RTLIL::SigBit y_bit = c->getPort(ID(Y));
+                               RTLIL::SigBit a_bit = c->getPort(ID::A);
+                               RTLIL::SigBit y_bit = c->getPort(ID::Y);
                                bit_users[a_bit].insert(c->name);
                                bit_drivers[y_bit].insert(c->name);
 
                                if (!a_bit.wire) {
-                                       c->setPort(ID(Y), module->addWire(NEW_ID));
+                                       c->setPort(ID::Y, module->addWire(NEW_ID));
                                        RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
                                        log_assert(wire);
                                        module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@@ -602,7 +602,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                                                RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
                                                                RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
                                                                RTLIL::Const::from_string("01"));
-                                               bit2sinks[cell->getPort(ID(A))].push_back(cell);
+                                               bit2sinks[cell->getPort(ID::A)].push_back(cell);
                                                cell_stats[ID($lut)]++;
                                        }
                                        else
@@ -618,9 +618,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
                        RTLIL::Cell *existing_cell = nullptr;
                        if (c->type == ID($lut)) {
-                               if (GetSize(c->getPort(ID(A))) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
-                                       SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID(A)).as_wire()->name));
-                                       SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID(Y)).as_wire()->name));
+                               if (GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
+                                       SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID::A).as_wire()->name));
+                                       SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID::Y).as_wire()->name));
                                        module->connect(my_y, my_a);
                                        if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx;
                                        log_abort();
@@ -694,30 +694,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                int in_wires = 0, out_wires = 0;
 
                // Stitch in mapped_mod's inputs/outputs into module
-               for (auto &it : mapped_mod->wires_) {
-                       RTLIL::Wire *w = it.second;
-                       if (!w->port_input && !w->port_output)
-                               continue;
-                       RTLIL::Wire *wire = module->wire(w->name);
+               for (auto port : mapped_mod->ports) {
+                       RTLIL::Wire *w = mapped_mod->wire(port);
+                       RTLIL::Wire *wire = module->wire(port);
                        log_assert(wire);
-                       RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
+                       RTLIL::Wire *remap_wire = module->wire(remap_name(port));
                        RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
                        log_assert(GetSize(signal) >= GetSize(remap_wire));
 
-                       log_assert(w->port_input || w->port_output);
                        RTLIL::SigSig conn;
-                       if (w->port_input) {
-                               conn.first = remap_wire;
-                               conn.second = signal;
-                               in_wires++;
-                               module->connect(conn);
-                       }
                        if (w->port_output) {
                                conn.first = signal;
                                conn.second = remap_wire;
                                out_wires++;
                                module->connect(conn);
                        }
+                       else if (w->port_input) {
+                               conn.first = remap_wire;
+                               conn.second = signal;
+                               in_wires++;
+                               module->connect(conn);
+                       }
                }
 
                for (auto &it : bit_users)
@@ -725,7 +722,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                for (auto driver_cell : bit_drivers.at(it.first))
                                for (auto user_cell : it.second)
                                        toposort.edge(driver_cell, user_cell);
-               bool no_loops = toposort.sort();
+               bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
                log_assert(no_loops);
 
                for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
@@ -737,8 +734,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        if (it == not2drivers.end())
                                continue;
                        RTLIL::Cell *driver_lut = it->second;
-                       RTLIL::SigBit a_bit = not_cell->getPort(ID(A));
-                       RTLIL::SigBit y_bit = not_cell->getPort(ID(Y));
+                       RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
+                       RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
                        RTLIL::Const driver_mask;
 
                        a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
@@ -754,7 +751,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
                        // Push downstream LUTs past inverter
                        for (auto sink_cell : jt->second) {
-                               SigSpec A = sink_cell->getPort(ID(A));
+                               SigSpec A = sink_cell->getPort(ID::A);
                                RTLIL::Const mask = sink_cell->getParam(ID(LUT));
                                int index = 0;
                                for (; index < GetSize(A); index++)
@@ -768,7 +765,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                        i += 1 << (index+1);
                                }
                                A[index] = y_bit;
-                               sink_cell->setPort(ID(A), A);
+                               sink_cell->setPort(ID::A, A);
                                sink_cell->setParam(ID(LUT), mask);
                        }
 
@@ -784,10 +781,10 @@ clone_lut:
                                else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
                        }
                        auto cell = module->addLut(NEW_ID,
-                                       driver_lut->getPort(ID(A)),
+                                       driver_lut->getPort(ID::A),
                                        y_bit,
                                        driver_mask);
-                       for (auto &bit : cell->connections_.at(ID(A))) {
+                       for (auto &bit : cell->connections_.at(ID::A)) {
                                bit.wire = module->wires_.at(remap_name(bit.wire->name));
                                bit2sinks[bit].push_back(cell);
                        }
@@ -1300,9 +1297,6 @@ struct Abc9Pass : public Pass {
 
                assign_map.clear();
 
-               // The "clean" pass also contains a design->check() call
-               Pass::call(design, "clean");
-
                log_pop();
        }
 } Abc9Pass;