* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
// Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
// http://www.eecs.berkeley.edu/~alanmi/abc/
-// [[CITE]] Berkeley Logic Interchange Format (BLIF)
-// University of California. Berkeley. July 28, 1992
-// http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
-
-// [[CITE]] Kahn's Topological sorting algorithm
-// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
-// http://en.wikipedia.org/wiki/Topological_sorting
-
#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
//#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
if (!cleanup)
tempdir_name[0] = tempdir_name[4] = '_';
tempdir_name = make_temp_dir(tempdir_name);
- log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
+ log_header(design, "Extracting gate netlist of module `%s' to `%s/input.aig'..\n",
module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
- std::string abc_script = stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
+ std::string abc_script = stringf("read %s/input.aig; &get -n; ", tempdir_name.c_str());
if (!liberty_file.empty()) {
abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
- abc_script += stringf("; &ps; &write %s/output.xaig", tempdir_name.c_str());
+ abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
abc_script = add_echos_to_abc_cmd(abc_script);
for (size_t i = 0; i+1 < abc_script.size(); i++)
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
- Pass::call(design, "aigmap; clean;");
+ Pass::call(design, "aigmap");
handle_loops(design);
- Pass::call(design, stringf("write_xaiger -O -symbols %s/input.xaig; ", tempdir_name.c_str()));
+ Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str()));
design->selection_stack.pop_back();
}
module->fixup_ports();
+ //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
+ // count_gates, GetSize(signal_list), count_input, count_output);
+
log_push();
//if (count_output > 0)
if (ret != 0)
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
- buffer = stringf("%s/%s", tempdir_name.c_str(), "output.xaig");
+ buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
std::ifstream ifs;
ifs.open(buffer);
if (ifs.fail())
bool builtin_lib = liberty_file.empty();
RTLIL::Design *mapped_design = new RTLIL::Design;
//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
- AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", "", true /* wideports */);
+ AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */);
reader.parse_xaiger();
ifs.close();
RTLIL::Wire *w = it.second;
RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
- design->select(module, remap_wire);
if (w->port_output) {
RTLIL::Wire *wire = module->wire(w->name);
if (wire) {
goto cleanup;
}
+ // Attempt another wideports_split here because there
+ // exists the possibility that different bits of a port
+ // could be an input and output, therefore parse_xiager()
+ // could not combine it into a wideport
auto r = wideports_split(w->name.str());
wire = module->wire(r.first);
log_assert(wire);
cell_stats[RTLIL::unescape_id(c->type)]++;
}
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
- design->select(module, cell);
continue;
}
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
- design->select(module, cell);
continue;
}
if (c->type == "\\MUX") {
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
- design->select(module, cell);
continue;
}
if (c->type == "\\MUX4") {
cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
- design->select(module, cell);
continue;
}
if (c->type == "\\MUX8") {
cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
- design->select(module, cell);
continue;
}
if (c->type == "\\MUX16") {
cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
- design->select(module, cell);
continue;
}
if (c->type == "\\AOI3" || c->type == "\\OAI3") {
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
- design->select(module, cell);
continue;
}
if (c->type == "\\AOI4" || c->type == "\\OAI4") {
cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
- design->select(module, cell);
continue;
}
if (c->type == "\\DFF") {
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
cell->setPort("\\C", clk_sig);
- design->select(module, cell);
continue;
}
}
cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
cell->setPort("\\C", clk_sig);
- design->select(module, cell);
continue;
}
}
cell->setPort(conn.first, newsig);
}
- design->select(module, cell);
}
// Copy connections (and rename) from mapped_mod to module
signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
}
else {
+ // Attempt another wideports_split here because there
+ // exists the possibility that different bits of a port
+ // could be an input and output, therefore parse_xiager()
+ // could not combine it into a wideport
auto r = wideports_split(w->name.str());
wire = module->wire(r.first);
log_assert(wire);
}
log_assert(GetSize(signal) >= GetSize(remap_wire));
+ log_assert(w->port_input || w->port_output);
+ RTLIL::SigSig conn;
if (w->port_input) {
- RTLIL::SigSig conn;
conn.first = remap_wire;
conn.second = signal;
in_wires++;
module->connect(conn);
}
- else if (w->port_output) {
- RTLIL::SigSig conn;
+ if (w->port_output) {
conn.first = signal;
conn.second = remap_wire;
out_wires++;
module->connect(conn);
}
- else log_abort();
}
//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
// log("Don't call ABC as there is nothing to map.\n");
//}
- Pass::call(design, "clean");
-
cleanup:
if (cleanup)
{
}
}
+ Pass::call(design, "clean");
+
assign_map.clear();
signal_map.clear();
signal_init.clear();
projects / yosys.git / blobdiff