Merge remote-tracking branch 'origin/master' into xaig

[yosys.git] / passes / techmap / abc9.cc

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 90234ea336215b0dba62cfa1a54b8e9273a912f6..da3d36354157110c644c2905a2d10adf123437b6 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
        handle_loops(design);
 
-    Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str()));
+       Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str()));
 
        design->selection_stack.pop_back();
 
@@ -523,8 +523,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                bool builtin_lib = liberty_file.empty();
                RTLIL::Design *mapped_design = new RTLIL::Design;
                //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
-               buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols");
-               AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */);
+               AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */);
                reader.parse_xaiger();
 
                ifs.close();
@@ -893,21 +892,20 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        }
                        log_assert(GetSize(signal) >= GetSize(remap_wire));
 
+                       log_assert(w->port_input || w->port_output);
+                       RTLIL::SigSig conn;
                        if (w->port_input) {
-                               RTLIL::SigSig conn;
                                conn.first = remap_wire;
                                conn.second = signal;
                                in_wires++;
                                module->connect(conn);
                        }
-                       else if (w->port_output) {
-                               RTLIL::SigSig conn;
+                       if (w->port_output) {
                                conn.first = signal;
                                conn.second = remap_wire;
                                out_wires++;
                                module->connect(conn);
                        }
-                       else log_abort();
                }
 
                //log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
@@ -1538,7 +1536,7 @@ struct Abc9Pass : public Pass {
                        }
                }
 
-        Pass::call(design, "clean");
+               Pass::call(design, "clean");
 
                assign_map.clear();
                signal_map.clear();