Merge remote-tracking branch 'origin/master' into xaig

[yosys.git] / passes / techmap / abc9.cc

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index de47de92e5433541565f7168dc499603dc2a0364..da3d36354157110c644c2905a2d10adf123437b6 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
        handle_loops(design);
 
-    Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str()));
+       Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str()));
 
        design->selection_stack.pop_back();
 
@@ -898,13 +898,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                conn.first = remap_wire;
                                conn.second = signal;
                                in_wires++;
+                               module->connect(conn);
                        }
                        if (w->port_output) {
                                conn.first = signal;
                                conn.second = remap_wire;
                                out_wires++;
+                               module->connect(conn);
                        }
-                       module->connect(conn);
                }
 
                //log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
@@ -1535,7 +1536,7 @@ struct Abc9Pass : public Pass {
                        }
                }
 
-        Pass::call(design, "clean");
+               Pass::call(design, "clean");
 
                assign_map.clear();
                signal_map.clear();