#include "kernel/utils.h"
#include "kernel/celltypes.h"
+#define ABC9_FLOPS_BASE_ID 8000
#define ABC9_DELAY_BASE_ID 9000
USING_YOSYS_NAMESPACE
{
dict<IdString,IdString> box_lookup;
for (auto m : design->modules()) {
+ if (m->name.begins_with("$paramod"))
+ continue;
+
auto flop = m->get_bool_attribute(ID(abc9_flop));
auto it = m->attributes.find(ID(abc9_box_id));
- if (it == m->attributes.end()) {
- if (flop)
- log_error("Module '%s' contains (* abc9_flop *) but not (* abc9_box_id=<int> *).\n", log_id(m));
- continue;
+ if (!flop) {
+ if (it == m->attributes.end())
+ continue;
+ auto id = it->second.as_int();
+ auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
+ if (!r.second)
+ log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+ log_id(m), id, log_id(r.first->second));
}
- if (m->name.begins_with("$paramod"))
- continue;
- auto id = it->second.as_int();
- auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
- if (!r.second)
- log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
- log_id(m), id, log_id(r.first->second));
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
}
}
-void break_scc(RTLIL::Module *module)
+void mark_scc(RTLIL::Module *module)
{
// For every unique SCC found, (arbitrarily) find the first
// cell in the component, and convert all wires driven by
auto it = cell->attributes.find(ID(abc9_scc_id));
if (it == cell->attributes.end())
continue;
- auto r = ids_seen.insert(it->second);
+ auto id = it->second;
+ auto r = ids_seen.insert(id);
cell->attributes.erase(it);
if (!r.second)
continue;
if (cell->output(c.first)) {
SigBit b = c.second.as_bit();
Wire *w = b.wire;
- if (w->port_input) {
- // In this case, hopefully the loop break has been already created
- // Get the non-prefixed wire
- Wire *wo = module->wire(stringf("%s.abco", b.wire->name.c_str()));
- log_assert(wo != nullptr);
- log_assert(wo->port_output);
- log_assert(b.offset < GetSize(wo));
- c.second = RTLIL::SigBit(wo, b.offset);
- }
- else {
- // Create a new output/input loop break
- w->port_input = true;
- w = module->wire(stringf("%s.abco", w->name.c_str()));
- if (!w) {
- w = module->addWire(stringf("%s.abco", b.wire->name.c_str()), GetSize(b.wire));
- w->port_output = true;
- }
- else {
- log_assert(w->port_input);
- log_assert(b.offset < GetSize(w));
- }
- w->set_bool_attribute(ID(abc9_scc_break));
- c.second = RTLIL::SigBit(w, b.offset);
- }
+ w->set_bool_attribute(ID::keep);
+ w->attributes[ID(abc9_scc_id)] = id.as_int();
}
}
}
module->fixup_ports();
}
-void unbreak_scc(RTLIL::Module *module)
-{
- // Now 'unexpose' those wires by undoing
- // the expose operation -- remove them from PO/PI
- // and re-connecting them back together
- for (auto wire : module->wires()) {
- auto it = wire->attributes.find(ID(abc9_scc_break));
- if (it != wire->attributes.end()) {
- wire->attributes.erase(it);
- log_assert(wire->port_output);
- wire->port_output = false;
- std::string name = wire->name.str();
- RTLIL::Wire *i_wire = module->wire(name.substr(0, GetSize(name) - 5));
- log_assert(i_wire);
- log_assert(i_wire->port_input);
- i_wire->port_input = false;
- module->connect(i_wire, wire);
- }
- }
- module->fixup_ports();
-}
-
void prep_dff(RTLIL::Module *module)
{
auto design = module->design;
}
}
-void prep_holes(RTLIL::Module *module, bool dff)
+void prep_xaiger(RTLIL::Module *module, bool dff)
{
auto design = module->design;
log_assert(design);
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
- bool abc9_box_seen = false;
+ dict<IdString, std::vector<IdString>> box_ports;
for (auto cell : module->cells()) {
if (cell->type == "$__ABC9_FF_")
continue;
auto inst_module = module->design->module(cell->type);
- bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
- bool abc9_flop = false;
- if (abc9_box) {
- abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
- if (abc9_flop && !dff)
- continue;
- abc9_box_seen = abc9_box;
+ bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
+ if (abc9_flop && !dff)
+ continue;
+
+ if ((inst_module && inst_module->attributes.count("\\abc9_box_id")) || abc9_flop) {
+ auto r = box_ports.insert(cell->type);
+ if (r.second) {
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : inst_module->ports) {
+ auto w = inst_module->wire(port_name);
+ log_assert(w);
+ if (w->get_bool_attribute("\\abc9_carry")) {
+ log_assert(w->port_input != w->port_output);
+ if (w->port_input)
+ carry_in = port_name;
+ else if (w->port_output)
+ carry_out = port_name;
+ }
+ else
+ r.first->second.push_back(port_name);
+ }
+ if (carry_in != IdString()) {
+ r.first->second.push_back(carry_in);
+ r.first->second.push_back(carry_out);
+ }
+ }
}
else if (!yosys_celltypes.cell_known(cell->type))
continue;
toposort.node(cell->name);
}
- if (!abc9_box_seen)
+ if (box_ports.empty())
return;
for (auto &it : bit_users)
log_assert(no_loops);
- vector<Cell*> box_list;
+ RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
+ log_assert(holes_module);
+ holes_module->set_bool_attribute("\\abc9_holes");
+
+ dict<IdString, Cell*> cell_cache;
+
+ int port_id = 1, box_count = 0;
for (auto cell_name : toposort.sorted) {
RTLIL::Cell *cell = module->cell(cell_name);
log_assert(cell);
if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
continue;
- bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
-
- // Fully pad all unused input connections of this box cell with S0
- // Fully pad all undriven output connections of this box cell with anonymous wires
- for (const auto &port_name : box_module->ports) {
- RTLIL::Wire* w = box_module->wire(port_name);
- log_assert(w);
- auto it = cell->connections_.find(port_name);
- if (w->port_input) {
- RTLIL::SigSpec rhs;
- if (it != cell->connections_.end()) {
- if (GetSize(it->second) < GetSize(w))
- it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
- rhs = it->second;
- }
- else {
- rhs = RTLIL::SigSpec(State::S0, GetSize(w));
- cell->setPort(port_name, rhs);
- }
- }
- if (w->port_output) {
- RTLIL::SigSpec rhs;
- auto it = cell->connections_.find(w->name);
- if (it != cell->connections_.end()) {
- if (GetSize(it->second) < GetSize(w))
- it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
- rhs = it->second;
- }
- else {
- Wire *wire = module->addWire(NEW_ID, GetSize(w));
- if (blackbox)
- wire->set_bool_attribute(ID(abc9_padding));
- rhs = wire;
- cell->setPort(port_name, rhs);
- }
- }
- }
+ cell->attributes["\\abc9_box_seq"] = box_count++;
- cell->attributes["\\abc9_box_seq"] = box_list.size();
- //log_debug("%s.%s is box %d\n", log_id(module), log_id(cell), box_list.size());
- box_list.emplace_back(cell);
- }
- log_assert(!box_list.empty());
+ IdString derived_type = box_module->derive(design, cell->parameters);
+ box_module = design->module(derived_type);
- RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
- log_assert(holes_module);
- holes_module->set_bool_attribute("\\abc9_holes");
-
- dict<IdString, Cell*> cell_cache;
- dict<IdString, std::vector<IdString>> box_ports;
-
- int port_id = 1;
- for (auto cell : box_list) {
- RTLIL::Module* orig_box_module = design->module(cell->type);
- log_assert(orig_box_module);
- IdString derived_name = orig_box_module->derive(design, cell->parameters);
- RTLIL::Module* box_module = design->module(derived_name);
- //cell->type = derived_name;
- //cell->parameters.clear();
-
- auto r = cell_cache.insert(derived_name);
+ auto r = cell_cache.insert(derived_type);
auto &holes_cell = r.first->second;
if (r.second) {
- auto r2 = box_ports.insert(cell->type);
- if (r2.second) {
- // Make carry in the last PI, and carry out the last PO
- // since ABC requires it this way
- IdString carry_in, carry_out;
- for (const auto &port_name : box_module->ports) {
- auto w = box_module->wire(port_name);
- log_assert(w);
- if (w->get_bool_attribute("\\abc9_carry")) {
- if (w->port_input)
- carry_in = port_name;
- if (w->port_output)
- carry_out = port_name;
- }
- else
- r2.first->second.push_back(port_name);
- }
-
- if (carry_in != IdString()) {
- r2.first->second.push_back(carry_in);
- r2.first->second.push_back(carry_out);
- }
- }
+ if (box_module->has_processes())
+ Pass::call_on_module(design, box_module, "proc");
if (box_module->get_bool_attribute("\\whitebox")) {
- holes_cell = holes_module->addCell(cell->name, derived_name);
+ holes_cell = holes_module->addCell(cell->name, derived_type);
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc");
}
}
else if (w->port_output)
- conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
+ conn = holes_module->addWire(stringf("%s.%s", derived_type.c_str(), log_id(port_name)), GetSize(w));
}
// For flops only, create an extra 1-bit input that drives a new wire
}
}
-void prep_times(RTLIL::Design *design)
+void prep_delays(RTLIL::Design *design)
{
std::set<int> delays;
pool<Module*> flops;
- std::vector<Cell*> boxes;
- std::map<int,std::vector<int>> requireds;
+ std::vector<Cell*> cells;
+ dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
for (auto module : design->selected_modules()) {
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(module));
continue;
}
- boxes.clear();
+ cells.clear();
for (auto cell : module->cells()) {
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
continue;
if (!inst_module->get_blackbox_attribute())
continue;
if (inst_module->get_bool_attribute(ID(abc9_flop))) {
+ IdString derived_type = inst_module->derive(design, cell->parameters);
+ inst_module = design->module(derived_type);
+ log_assert(inst_module);
flops.insert(inst_module);
- continue;
+ continue; // because all flop required times
+ // will be captured in the flop box
}
- // All remaining boxes are combinatorial and cannot
- // contain a required time
if (inst_module->attributes.count(ID(abc9_box_id)))
continue;
- boxes.emplace_back(cell);
+ cells.emplace_back(cell);
}
delays.clear();
- requireds.clear();
- for (auto cell : boxes) {
+ for (auto cell : cells) {
RTLIL::Module* inst_module = module->design->module(cell->type);
log_assert(inst_module);
+ auto &cell_requireds = requireds_cache[cell->type];
for (auto &conn : cell->connections_) {
auto port_wire = inst_module->wire(conn.first);
if (!port_wire->port_input)
continue;
- auto it = port_wire->attributes.find("\\abc9_required");
- if (it == port_wire->attributes.end())
- continue;
-
- int count = 0;
- requireds.clear();
- if (it->second.flags == 0) {
- count = 1;
- requireds[it->second.as_int()].push_back(0);
+ auto r = cell_requireds.insert(conn.first);
+ auto &requireds = r.first->second;
+ if (r.second) {
+ auto it = port_wire->attributes.find("\\abc9_required");
+ if (it == port_wire->attributes.end())
+ continue;
+ if (it->second.flags == 0) {
+ int delay = it->second.as_int();
+ delays.insert(delay);
+ requireds.emplace_back(delay);
+ }
+ else
+ for (const auto &tok : split_tokens(it->second.decode_string())) {
+ int delay = atoi(tok.c_str());
+ delays.insert(delay);
+ requireds.push_back(delay);
+ }
}
- else
- for (const auto &tok : split_tokens(it->second.decode_string()))
- requireds[atoi(tok.c_str())].push_back(count++);
- if (count > 1 && count != GetSize(port_wire))
+
+ if (requireds.empty())
+ continue;
+ if (GetSize(requireds) > 1 && GetSize(requireds) != GetSize(port_wire))
log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
- GetSize(port_wire), log_signal(it->second), count);
+ GetSize(port_wire), log_signal(port_wire->attributes.at("\\abc9_required")), GetSize(requireds));
SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
- for (const auto &i : requireds) {
+ auto it = requireds.begin();
+ for (int i = 0; i < GetSize(conn.second); ++i) {
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
- if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), i.first);
+ if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
}
#endif
- delays.insert(i.first);
- for (auto offset : i.second) {
- auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
- box->setPort(ID(I), conn.second[offset]);
- box->setPort(ID(O), O[offset]);
- box->setParam(ID(DELAY), i.first);
- conn.second[offset] = O[offset];
- }
+ auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
+ box->setPort(ID(I), conn.second[i]);
+ box->setPort(ID(O), O[i]);
+ box->setParam(ID(DELAY), *it);
+ if (requireds.size() > 1)
+ it++;
+ conn.second[i] = O[i];
}
}
}
module->attributes[ID(abc9_delays)] = ss.str();
}
+ int flops_id = ABC9_FLOPS_BASE_ID;
std::stringstream ss;
for (auto flop_module : flops) {
- // Skip parameterised flop_modules for now (since we do not
- // dynamically generate the abc9_box_id)
- if (flop_module->name.begins_with("$paramod"))
- continue;
-
int num_inputs = 0, num_outputs = 0;
for (auto port_name : flop_module->ports) {
auto wire = flop_module->wire(port_name);
}
log_assert(num_outputs == 1);
- ss << log_id(flop_module) << " " << flop_module->attributes.at(ID(abc9_box_id)).as_int();
+ auto r = flop_module->attributes.insert(ID(abc9_box_id));
+ if (r.second)
+ r.first->second = flops_id++;
+
+ ss << log_id(flop_module) << " " << r.first->second.as_int();
ss << " 1 " << num_inputs+1 << " " << num_outputs << std::endl;
bool first = true;
for (auto port_name : flop_module->ports) {
for (auto w : mapped_mod->wires())
module->addWire(remap_name(w->name), GetSize(w));
- dict<IdString,IdString> box_lookup;
- for (auto m : design->modules()) {
- auto it = m->attributes.find(ID(abc9_box_id));
- if (it == m->attributes.end())
- continue;
- if (m->name.begins_with("$paramod"))
- continue;
- auto id = it->second.as_int();
- auto r YS_ATTRIBUTE(unused) = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
- log_assert(r.second);
- }
-
- pool<IdString> delay_boxes;
std::vector<Cell*> boxes;
for (auto cell : module->cells().to_vector()) {
+ if (cell->has_keep_attr())
+ continue;
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
module->remove(cell);
- else if (cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY=")) {
- delay_boxes.insert(cell->name);
- module->remove(cell);
- }
else if (cell->attributes.erase("\\abc9_box_seq"))
boxes.emplace_back(cell);
}
RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
bit_users[a_bit].insert(mapped_cell->name);
- bit_drivers[y_bit].insert(mapped_cell->name);
+ // Ignore inouts for topo ordering
+ if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
+ bit_drivers[y_bit].insert(mapped_cell->name);
if (!a_bit.wire) {
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
// (TODO: Optimise by not cloning unless will increase depth)
RTLIL::IdString driver_name;
if (GetSize(a_bit.wire) == 1)
- driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
+ driver_name = stringf("$lut%s", a_bit.wire->name.c_str());
else
- driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
+ driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset);
driver_lut = mapped_mod->cell(driver_name);
}
if (!driver_lut) {
// If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT
- RTLIL::Cell *cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
+ RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())),
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
}
if (cell->output(mapped_conn.first))
for (auto i : mapped_conn.second)
- bit_drivers[i].insert(mapped_cell->name);
+ // Ignore inouts for topo ordering
+ if (i.wire && !(i.wire->port_input && i.wire->port_output))
+ bit_drivers[i].insert(mapped_cell->name);
}
}
- else if (delay_boxes.count(mapped_cell->name)) {
- SigBit I = mapped_cell->getPort(ID(i));
- SigBit O = mapped_cell->getPort(ID(o));
- if (I.wire)
- I.wire = module->wires_.at(remap_name(I.wire->name));
- log_assert(O.wire);
- O.wire = module->wires_.at(remap_name(O.wire->name));
- module->connect(O, I);
- continue;
- }
else {
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
- log_assert(existing_cell);
- log_assert(mapped_cell->type.begins_with("$__boxid"));
-
- auto type = box_lookup.at(mapped_cell->type, IdString());
- if (type == IdString())
- log_error("No module with abc9_box_id = %s found.\n", mapped_cell->type.c_str() + strlen("$__boxid"));
- mapped_cell->type = type;
+ if (!existing_cell)
+ log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
+#ifndef NDEBUG
+ RTLIL::Module* box_module = design->module(existing_cell->type);
+ IdString derived_type = box_module->derive(design, existing_cell->parameters);
+ RTLIL::Module* derived_module = design->module(derived_type);
+ log_assert(derived_module);
+ log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
+#endif
+ mapped_cell->type = existing_cell->type;
+
+ if (mapped_cell->type == ID($__ABC9_DELAY)) {
+ SigBit I = mapped_cell->getPort(ID(i));
+ SigBit O = mapped_cell->getPort(ID(o));
+ if (I.wire)
+ I.wire = module->wires_.at(remap_name(I.wire->name));
+ log_assert(O.wire);
+ O.wire = module->wires_.at(remap_name(O.wire->name));
+ module->connect(O, I);
+ continue;
+ }
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = existing_cell->parameters;
SigSpec outputs = std::move(it->second);
mapped_cell->connections_.erase(it);
- RTLIL::Module* box_module = design->module(mapped_cell->type);
auto abc9_flop = box_module->attributes.count("\\abc9_flop");
if (!abc9_flop) {
for (const auto &i : inputs)
bit_users[i].insert(mapped_cell->name);
for (const auto &i : outputs)
- bit_drivers[i].insert(mapped_cell->name);
+ // Ignore inouts for topo ordering
+ if (i.wire && !(i.wire->port_input && i.wire->port_output))
+ bit_drivers[i].insert(mapped_cell->name);
}
auto r2 = box_ports.insert(cell->type);
auto w = box_module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
+ log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
- if (w->port_output)
+ else if (w->port_output)
carry_out = port_name;
}
else
c.wire = module->wires_.at(remap_name(c.wire->name));
newsig.append(c);
}
-
- auto it = existing_cell->connections_.find(port_name);
- if (it == existing_cell->connections_.end())
- continue;
- if (GetSize(newsig) > GetSize(it->second))
- newsig = newsig.extract(0, GetSize(it->second));
- else
- log_assert(GetSize(newsig) == GetSize(it->second));
-
cell->setPort(port_name, newsig);
if (w->port_input && !abc9_flop)
// Stitch in mapped_mod's inputs/outputs into module
for (auto port : mapped_mod->ports) {
- RTLIL::Wire *w = mapped_mod->wire(port);
+ RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
+ if (wire->attributes.erase(ID(abc9_scc_id))) {
+ auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
+ log_assert(r);
+ }
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire));
RTLIL::SigSig conn;
- if (w->port_output) {
+ if (mapped_wire->port_output) {
conn.first = signal;
conn.second = remap_wire;
out_wires++;
module->connect(conn);
}
- else if (w->port_input) {
+ else if (mapped_wire->port_input) {
conn.first = remap_wire;
conn.second = signal;
in_wires++;
log("\n");
log(" abc9_ops [options] [selection]\n");
log("\n");
+ log("This pass contains a set of supporting operations for use during ABC technology\n");
+ log("mapping, and is expected to be called in conjunction with other operations from\n");
+ log("the `abc9' script pass. Only fully-selected modules are supported.\n");
+ log("\n");
+ log(" -check\n");
+ log(" check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
+ log(" (* abc9_carry *) is only given for one input/output port, etc.\n");
+ log("\n");
+ log(" -prep_delays\n");
+ log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
+ log(" certain delays, e.g. (* abc9_required *) values.\n");
+ log("\n");
+ log(" -mark_scc\n");
+ log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n");
+ log(" (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
+ log(" wires driven by this cell's outputs with a (* keep *) attribute in order\n");
+ log(" to break the SCC. this temporary attribute will be removed on -reintegrate.\n");
+ log("\n");
+ log(" -prep_xaiger\n");
+ log(" prepare the design for XAIGER output. this includes computing the\n");
+ log(" topological ordering of ABC9 boxes, as well as preparing the\n");
+ log(" '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
+ log(" whiteboxes.\n");
+ log("\n");
+ log(" -dff\n");
+ log(" consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
+ log(" during -prep_xaiger.\n");
+ log("\n");
+ log(" -prep_dff\n");
+ log(" compute the clock domain and initial value of each flop in the design.\n");
+ log(" process the '$holes' module to support clock-enable functionality.\n");
+ log("\n");
+ log(" -write_box (<src>|(null)) <dst>\n");
+ log(" copy the existing box file from <src> (skip if '(null)') and append any\n");
+ log(" new box definitions.\n");
+ log("\n");
+ log(" -reintegrate\n");
+ log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n");
+ log(" by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
+ log(" inputs and outputs.\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
bool check_mode = false;
- bool prep_times_mode = false;
- bool break_scc_mode = false;
- bool unbreak_scc_mode = false;
- bool prep_holes_mode = false;
+ bool prep_delays_mode = false;
+ bool mark_scc_mode = false;
bool prep_dff_mode = false;
- std::string write_box_src, write_box_dst;
+ bool prep_xaiger_mode = false;
bool reintegrate_mode = false;
bool dff_mode = false;
+ std::string write_box_src, write_box_dst;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
check_mode = true;
continue;
}
- if (arg == "-break_scc") {
- break_scc_mode = true;
- continue;
- }
- if (arg == "-unbreak_scc") {
- unbreak_scc_mode = true;
+ if (arg == "-mark_scc") {
+ mark_scc_mode = true;
continue;
}
if (arg == "-prep_dff") {
prep_dff_mode = true;
continue;
}
- if (arg == "-prep_holes") {
- prep_holes_mode = true;
+ if (arg == "-prep_xaiger") {
+ prep_xaiger_mode = true;
continue;
}
- if (arg == "-prep_times") {
- prep_times_mode = true;
+ if (arg == "-prep_delays") {
+ prep_delays_mode = true;
continue;
}
if (arg == "-write_box" && argidx+2 < args.size()) {
}
extra_args(args, argidx, design);
- if (!(check_mode || break_scc_mode || unbreak_scc_mode || prep_times_mode || prep_holes_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
- log_cmd_error("At least one of -check, -{,un}break_scc, -prep_{times,holes,dff}, -write_box, -reintegrate must be specified.\n");
+ if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
+ log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff}, -write_box, -reintegrate must be specified.\n");
- if (dff_mode && !prep_holes_mode)
- log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
+ if (dff_mode && !prep_xaiger_mode)
+ log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
if (check_mode)
check(design);
- if (prep_times_mode)
- prep_times(design);
+ if (prep_delays_mode)
+ prep_delays(design);
for (auto mod : design->selected_modules()) {
if (mod->get_bool_attribute("\\abc9_holes"))
if (!design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
- if (break_scc_mode)
- break_scc(mod);
- if (unbreak_scc_mode)
- unbreak_scc(mod);
- if (prep_holes_mode)
- prep_holes(mod, dff_mode);
- if (prep_dff_mode)
- prep_dff(mod);
if (!write_box_src.empty())
write_box(mod, write_box_src, write_box_dst);
+ if (mark_scc_mode)
+ mark_scc(mod);
+ if (prep_dff_mode)
+ prep_dff(mod);
+ if (prep_xaiger_mode)
+ prep_xaiger(mod, dff_mode);
if (reintegrate_mode)
reintegrate(mod);
}
projects / yosys.git / blobdiff