#include "kernel/sigtools.h"
#include "kernel/utils.h"
#include "kernel/celltypes.h"
+#include "kernel/timinginfo.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
}
-void break_scc(RTLIL::Module *module)
+void check(RTLIL::Design *design)
+{
+ dict<IdString,IdString> box_lookup;
+ for (auto m : design->modules()) {
+ if (m->name.begins_with("$paramod"))
+ continue;
+
+ auto flop = m->get_bool_attribute(ID(abc9_flop));
+ auto it = m->attributes.find(ID(abc9_box_id));
+ if (!flop) {
+ if (it == m->attributes.end())
+ continue;
+ auto id = it->second.as_int();
+ auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
+ if (!r.second)
+ log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+ log_id(m), id, log_id(r.first->second));
+ }
+
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : m->ports) {
+ auto w = m->wire(port_name);
+ log_assert(w);
+ if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->port_input) {
+ if (carry_in != IdString())
+ log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
+ carry_in = port_name;
+ }
+ if (w->port_output) {
+ if (carry_out != IdString())
+ log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
+ carry_out = port_name;
+ }
+ }
+ }
+
+ if (carry_in != IdString() && carry_out == IdString())
+ log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
+ if (carry_in == IdString() && carry_out != IdString())
+ log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
+
+ if (flop) {
+ int num_outputs = 0;
+ for (auto port_name : m->ports) {
+ auto wire = m->wire(port_name);
+ if (wire->port_output) num_outputs++;
+ }
+ if (num_outputs != 1)
+ log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
+ }
+ }
+}
+
+void mark_scc(RTLIL::Module *module)
{
// For every unique SCC found, (arbitrarily) find the first
// cell in the component, and convert all wires driven by
auto it = cell->attributes.find(ID(abc9_scc_id));
if (it == cell->attributes.end())
continue;
- auto r = ids_seen.insert(it->second);
+ auto id = it->second;
+ auto r = ids_seen.insert(id);
cell->attributes.erase(it);
if (!r.second)
continue;
if (cell->output(c.first)) {
SigBit b = c.second.as_bit();
Wire *w = b.wire;
- if (w->port_input) {
- // In this case, hopefully the loop break has been already created
- // Get the non-prefixed wire
- Wire *wo = module->wire(stringf("%s.abco", b.wire->name.c_str()));
- log_assert(wo != nullptr);
- log_assert(wo->port_output);
- log_assert(b.offset < GetSize(wo));
- c.second = RTLIL::SigBit(wo, b.offset);
- }
- else {
- // Create a new output/input loop break
- w->port_input = true;
- w = module->wire(stringf("%s.abco", w->name.c_str()));
- if (!w) {
- w = module->addWire(stringf("%s.abco", b.wire->name.c_str()), GetSize(b.wire));
- w->port_output = true;
- }
- else {
- log_assert(w->port_input);
- log_assert(b.offset < GetSize(w));
- }
- w->set_bool_attribute(ID(abc9_scc_break));
- c.second = RTLIL::SigBit(w, b.offset);
- }
+ w->set_bool_attribute(ID::keep);
+ w->attributes[ID(abc9_scc_id)] = id.as_int();
}
}
}
module->fixup_ports();
}
-void unbreak_scc(RTLIL::Module *module)
-{
- // Now 'unexpose' those wires by undoing
- // the expose operation -- remove them from PO/PI
- // and re-connecting them back together
- for (auto wire : module->wires()) {
- auto it = wire->attributes.find(ID(abc9_scc_break));
- if (it != wire->attributes.end()) {
- wire->attributes.erase(it);
- log_assert(wire->port_output);
- wire->port_output = false;
- std::string name = wire->name.str();
- RTLIL::Wire *i_wire = module->wire(name.substr(0, GetSize(name) - 5));
- log_assert(i_wire);
- log_assert(i_wire->port_input);
- i_wire->port_input = false;
- module->connect(i_wire, wire);
- }
- }
- module->fixup_ports();
-}
-
void prep_dff(RTLIL::Module *module)
{
auto design = module->design;
clkdomain_t key(abc9_clock);
auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
- auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
- log_assert(r2.second);
-
- Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
- if (abc9_init_wire == NULL)
- log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
- log_assert(GetSize(abc9_init_wire) == 1);
- SigSpec abc9_init = assign_map(abc9_init_wire);
- if (!abc9_init.is_fully_const())
- log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
- r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
+ auto r2 = cell->attributes.insert(ID(abc9_mergeability));;
log_assert(r2.second);
+ r2.first->second = r.first->second;
}
RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
SigMap sigmap(holes_module);
dict<SigSpec, SigSpec> replace;
- for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
- auto cell = it->second;
- if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
- "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
- SigBit D = cell->getPort("\\D");
- SigBit Q = cell->getPort("\\Q");
- // Remove the $_DFF_* cell from what needs to be a combinatorial box
- it = holes_module->cells_.erase(it);
- Wire *port;
- if (GetSize(Q.wire) == 1)
- port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
- else
- port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
- log_assert(port);
- // Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
- // in order to extract just the combinatorial control logic that feeds the box
- // (i.e. clock enable, synchronous reset, etc.)
- replace.insert(std::make_pair(Q,D));
- // Since `flatten` above would have created wires named "<cell>.Q",
- // extract the pre-techmap cell name
- auto pos = Q.wire->name.str().rfind(".");
- log_assert(pos != std::string::npos);
- IdString driver = Q.wire->name.substr(0, pos);
- // And drive the signal that was previously driven by "DFF.Q" (typically
- // used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
- // wire (which itself is driven an by input port) we inserted above
- Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
- log_assert(currQ);
- holes_module->connect(Q, currQ);
- }
+ for (auto cell : holes_module->cells().to_vector()) {
+ if (!cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
+ "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_"))
+ continue;
+ SigBit D = cell->getPort("\\D");
+ SigBit Q = cell->getPort("\\Q");
+ // Emulate async control embedded inside $_DFF_* cell with mux in front of D
+ if (cell->type.in("$_DFF_NN0_", "$_DFF_PN0_"))
+ D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort("\\R"));
+ else if (cell->type.in("$_DFF_NN1_", "$_DFF_PN1_"))
+ D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort("\\R"));
+ else if (cell->type.in("$_DFF_NP0_", "$_DFF_PP0_"))
+ D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort("\\R"));
+ else if (cell->type.in("$_DFF_NP1_", "$_DFF_PP1_"))
+ D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort("\\R"));
+ // Remove the $_DFF_* cell from what needs to be a combinatorial box
+ holes_module->remove(cell);
+ Wire *port;
+ if (GetSize(Q.wire) == 1)
+ port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
else
- ++it;
+ port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
+ log_assert(port);
+ // Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
+ // in order to extract just the combinatorial control logic that feeds the box
+ // (i.e. clock enable, synchronous reset, etc.)
+ replace.insert(std::make_pair(Q,D));
+ // Since `flatten` above would have created wires named "<cell>.Q",
+ // extract the pre-techmap cell name
+ auto pos = Q.wire->name.str().rfind(".");
+ log_assert(pos != std::string::npos);
+ IdString driver = Q.wire->name.substr(0, pos);
+ // And drive the signal that was previously driven by "DFF.Q" (typically
+ // used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
+ // wire (which itself is driven an by input port) we inserted above
+ Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
+ log_assert(currQ);
+ holes_module->connect(Q, currQ);
}
for (auto &conn : holes_module->connections_)
}
}
-void prep_holes(RTLIL::Module *module, bool dff)
+void prep_xaiger(RTLIL::Module *module, bool dff)
{
auto design = module->design;
log_assert(design);
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
- bool abc9_box_seen = false;
+ dict<IdString, std::vector<IdString>> box_ports;
for (auto cell : module->cells()) {
if (cell->type == "$__ABC9_FF_")
continue;
+ if (cell->has_keep_attr())
+ continue;
auto inst_module = module->design->module(cell->type);
- bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
- bool abc9_flop = false;
- if (abc9_box) {
- abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
- if (abc9_flop && !dff)
- continue;
- abc9_box_seen = abc9_box;
+ bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
+ if (abc9_flop && !dff)
+ continue;
+
+ if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) {
+ auto r = box_ports.insert(cell->type);
+ if (r.second) {
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : inst_module->ports) {
+ auto w = inst_module->wire(port_name);
+ log_assert(w);
+ if (w->get_bool_attribute("\\abc9_carry")) {
+ log_assert(w->port_input != w->port_output);
+ if (w->port_input)
+ carry_in = port_name;
+ else if (w->port_output)
+ carry_out = port_name;
+ }
+ else
+ r.first->second.push_back(port_name);
+ }
+ if (carry_in != IdString()) {
+ r.first->second.push_back(carry_in);
+ r.first->second.push_back(carry_out);
+ }
+ }
}
else if (!yosys_celltypes.cell_known(cell->type))
continue;
+ // TODO: Speed up toposort -- we care about box ordering only
for (auto conn : cell->connections()) {
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
for (auto bit : sigmap(conn.second))
bit_drivers[bit].insert(cell->name);
}
-
toposort.node(cell->name);
}
- if (!abc9_box_seen)
+ if (box_ports.empty())
return;
for (auto &it : bit_users)
if (bit_drivers.count(it.first))
for (auto driver_cell : bit_drivers.at(it.first))
- for (auto user_cell : it.second)
- toposort.edge(driver_cell, user_cell);
+ for (auto user_cell : it.second)
+ toposort.edge(driver_cell, user_cell);
if (ys_debug(1))
toposort.analyze_loops = true;
log_assert(no_loops);
- vector<Cell*> box_list;
+ RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
+ log_assert(holes_module);
+ holes_module->set_bool_attribute("\\abc9_holes");
+
+ dict<IdString, Cell*> cell_cache;
+ TimingInfo timing;
+
+ int port_id = 1, box_count = 0;
for (auto cell_name : toposort.sorted) {
RTLIL::Cell *cell = module->cell(cell_name);
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
- if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
+ if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop")))
continue;
- bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
+ cell->attributes["\\abc9_box_seq"] = box_count++;
- // Fully pad all unused input connections of this box cell with S0
- // Fully pad all undriven output connections of this box cell with anonymous wires
- for (const auto &port_name : box_module->ports) {
- RTLIL::Wire* w = box_module->wire(port_name);
- log_assert(w);
- auto it = cell->connections_.find(port_name);
- if (w->port_input) {
- RTLIL::SigSpec rhs;
- if (it != cell->connections_.end()) {
- if (GetSize(it->second) < GetSize(w))
- it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
- rhs = it->second;
- }
- else {
- rhs = RTLIL::SigSpec(State::S0, GetSize(w));
- cell->setPort(port_name, rhs);
- }
- }
- if (w->port_output) {
- RTLIL::SigSpec rhs;
- auto it = cell->connections_.find(w->name);
- if (it != cell->connections_.end()) {
- if (GetSize(it->second) < GetSize(w))
- it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
- rhs = it->second;
- }
- else {
- Wire *wire = module->addWire(NEW_ID, GetSize(w));
- if (blackbox)
- wire->set_bool_attribute(ID(abc9_padding));
- rhs = wire;
- cell->setPort(port_name, rhs);
- }
- }
- }
-
- cell->attributes["\\abc9_box_seq"] = box_list.size();
- box_list.emplace_back(cell);
- }
- log_assert(!box_list.empty());
-
- RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
- log_assert(holes_module);
- holes_module->set_bool_attribute("\\abc9_holes");
-
- dict<IdString, Cell*> cell_cache;
- dict<IdString, std::vector<IdString>> box_ports;
+ IdString derived_type = box_module->derive(design, cell->parameters);
+ box_module = design->module(derived_type);
- int port_id = 1;
- for (auto cell : box_list) {
- RTLIL::Module* orig_box_module = design->module(cell->type);
- log_assert(orig_box_module);
- IdString derived_name = orig_box_module->derive(design, cell->parameters);
- RTLIL::Module* box_module = design->module(derived_name);
-
- auto r = cell_cache.insert(derived_name);
+ auto r = cell_cache.insert(derived_type);
auto &holes_cell = r.first->second;
if (r.second) {
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc");
- auto r2 = box_ports.insert(cell->type);
- if (r2.second) {
- // Make carry in the last PI, and carry out the last PO
- // since ABC requires it this way
- IdString carry_in, carry_out;
- for (const auto &port_name : box_module->ports) {
- auto w = box_module->wire(port_name);
- log_assert(w);
- if (w->get_bool_attribute("\\abc9_carry")) {
- if (w->port_input) {
- if (carry_in != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
- carry_in = port_name;
- }
- if (w->port_output) {
- if (carry_out != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
- carry_out = port_name;
- }
- }
- else
- r2.first->second.push_back(port_name);
- }
-
- if (carry_in != IdString() && carry_out == IdString())
- log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
- if (carry_in == IdString() && carry_out != IdString())
- log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
- if (carry_in != IdString()) {
- r2.first->second.push_back(carry_in);
- r2.first->second.push_back(carry_out);
- }
- }
-
if (box_module->get_bool_attribute("\\whitebox")) {
- holes_cell = holes_module->addCell(cell->name, derived_name);
+ holes_cell = holes_module->addCell(cell->name, derived_type);
+
+ if (box_module->has_processes())
+ Pass::call_on_module(design, box_module, "proc");
int box_inputs = 0;
for (auto port_name : box_ports.at(cell->type)) {
}
}
else if (w->port_output)
- conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
+ conn = holes_module->addWire(stringf("%s.%s", derived_type.c_str(), log_id(port_name)), GetSize(w));
}
// For flops only, create an extra 1-bit input that drives a new wire
}
}
-void reintegrate(RTLIL::Module *module)
+void prep_delays(RTLIL::Design *design, bool dff_mode)
{
- auto design = module->design;
- log_assert(design);
+ TimingInfo timing;
+
+ // Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
+ // (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
+ pool<Module*> flops;
+ std::vector<Cell*> cells;
+ for (auto module : design->selected_modules()) {
+ if (module->processes.size() > 0) {
+ log("Skipping module %s as it contains processes.\n", log_id(module));
+ continue;
+ }
- map_autoidx = autoidx++;
+ for (auto cell : module->cells()) {
+ if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
+ continue;
- RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
- if (mapped_mod == NULL)
- log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
+ RTLIL::Module* inst_module = module->design->module(cell->type);
+ if (!inst_module)
+ continue;
+ if (!inst_module->get_blackbox_attribute())
+ continue;
+ if (inst_module->attributes.count(ID(abc9_box)))
+ continue;
+ IdString derived_type = inst_module->derive(design, cell->parameters);
+ inst_module = design->module(derived_type);
+ log_assert(inst_module);
+
+ if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
+ flops.insert(inst_module);
+ continue; // do not add $__ABC9_DELAY boxes to flops
+ // as delays will be captured in the flop box
+ }
- for (auto w : mapped_mod->wires())
- module->addWire(remap_name(w->name), GetSize(w));
+ if (!timing.count(derived_type))
+ timing.setup_module(inst_module);
- dict<IdString,IdString> box_lookup;
- dict<IdString,std::vector<IdString>> box_ports;
+ cells.emplace_back(cell);
+ }
+ }
- for (auto m : design->modules()) {
- auto it = m->attributes.find(ID(abc9_box_id));
- if (it == m->attributes.end())
+ // Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
+ // with required times
+ for (auto cell : cells) {
+ auto module = cell->module;
+ RTLIL::Module* inst_module = module->design->module(cell->type);
+ log_assert(inst_module);
+ IdString derived_type = inst_module->derive(design, cell->parameters);
+ inst_module = design->module(derived_type);
+ log_assert(inst_module);
+
+ auto &t = timing.at(derived_type).required;
+ for (auto &conn : cell->connections_) {
+ auto port_wire = inst_module->wire(conn.first);
+ if (!port_wire->port_input)
+ continue;
+
+ SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
+ for (int i = 0; i < GetSize(conn.second); i++) {
+ auto d = t.at(SigBit(port_wire,i), 0);
+ if (d == 0)
+ continue;
+
+#ifndef NDEBUG
+ if (ys_debug(1)) {
+ static std::set<std::tuple<IdString,IdString,int>> seen;
+ if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n",
+ log_id(cell->type), log_id(conn.first), i, d);
+ }
+#endif
+ auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
+ box->setPort(ID(I), conn.second[i]);
+ box->setPort(ID(O), O[i]);
+ box->setParam(ID(DELAY), d);
+ conn.second[i] = O[i];
+ }
+ }
+ }
+}
+
+void prep_lut(RTLIL::Design *design, int maxlut)
+{
+ TimingInfo timing;
+
+ std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
+ for (auto module : design->modules()) {
+ auto it = module->attributes.find(ID(abc9_lut));
+ if (it == module->attributes.end())
continue;
- if (m->name.begins_with("$paramod"))
+
+ auto &t = timing.setup_module(module);
+
+ TimingInfo::NameBit o;
+ std::vector<int> specify;
+ for (const auto &i : t.comb) {
+ auto &d = i.first.second;
+ if (o == TimingInfo::NameBit())
+ o = d;
+ else if (o != d)
+ log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
+ specify.push_back(i.second);
+ }
+
+ if (maxlut && GetSize(specify) > maxlut)
continue;
- auto id = it->second.as_int();
- auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
- if (!r.second)
- log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
- log_id(m), id, log_id(r.first->second));
- log_assert(r.second);
+ // ABC requires non-decreasing LUT input delays
+ std::sort(specify.begin(), specify.end());
+ table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify));
+ }
+ // ABC requires ascending size
+ std::sort(table.begin(), table.end());
+
+ std::stringstream ss;
+ const auto &first = table.front();
+ // If the first entry does not start from a 1-input LUT,
+ // (as ABC requires) crop the first entry to do so
+ for (int i = 1; i < std::get<0>(first); i++) {
+ ss << "# $__ABC9_LUT" << i << std::endl;
+ ss << i << " " << std::get<2>(first);
+ for (int j = 0; j < i; j++)
+ ss << " " << std::get<3>(first)[j];
+ ss << std::endl;
+ }
+ for (const auto &i : table) {
+ ss << "# " << log_id(std::get<1>(i)) << std::endl;
+ ss << std::get<0>(i) << " " << std::get<2>(i);
+ for (const auto &j : std::get<3>(i))
+ ss << " " << j;
+ ss << std::endl;
+ }
+ design->scratchpad_set_string("abc9_ops.lut_library", ss.str());
+}
+
+void write_lut(RTLIL::Module *module, const std::string &dst) {
+ std::ofstream ofs(dst);
+ log_assert(ofs.is_open());
+ ofs << module->design->scratchpad_get_string("abc9_ops.lut_library");
+ ofs.close();
+}
+
+void prep_box(RTLIL::Design *design, bool dff_mode)
+{
+ TimingInfo timing;
+
+ std::stringstream ss;
+ int abc9_box_id = 1;
+ for (auto module : design->modules()) {
+ auto it = module->attributes.find(ID(abc9_box_id));
+ if (it == module->attributes.end())
+ continue;
+ abc9_box_id = std::max(abc9_box_id, it->second.as_int());
+ }
+
+ dict<IdString,std::vector<IdString>> box_ports;
+ for (auto module : design->modules()) {
+ auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
+ if (abc9_flop) {
+ auto r = module->attributes.insert(ID(abc9_box_id));
+ if (!r.second)
+ continue;
+ r.first->second = abc9_box_id++;
+
+ if (dff_mode) {
+ int num_inputs = 0, num_outputs = 0;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ log_assert(GetSize(wire) == 1);
+ if (wire->port_input) num_inputs++;
+ if (wire->port_output) num_outputs++;
+ }
+ log_assert(num_outputs == 1);
+
+ ss << log_id(module) << " " << r.first->second.as_int();
+ ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+ ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
+
+ ss << "#";
+ bool first = true;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ if (!wire->port_input)
+ continue;
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ ss << log_id(wire);
+ }
+ ss << " abc9_ff.Q" << std::endl;
+
+ auto &t = timing.setup_module(module).required;
+ first = true;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ if (!wire->port_input)
+ continue;
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ log_assert(GetSize(wire) == 1);
+ auto it = t.find(SigBit(wire,0));
+ if (it == t.end())
+ // Assume that no setup time means zero
+ ss << 0;
+ else {
+ ss << it->second;
+
+#ifndef NDEBUG
+ if (ys_debug(1)) {
+ static std::set<std::pair<IdString,IdString>> seen;
+ if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
+ log_id(port_name), it->second);
+ }
+#endif
+ }
- auto r2 = box_ports.insert(m->name);
- if (r2.second) {
+ }
+ // Last input is 'abc9_ff.Q'
+ ss << " 0" << std::endl << std::endl;
+ continue;
+ }
+ }
+ else {
+ if (!module->attributes.erase(ID(abc9_box)))
+ continue;
+
+ auto r = module->attributes.insert(ID(abc9_box_id));
+ if (!r.second)
+ continue;
+ r.first->second = abc9_box_id++;
+ }
+
+ auto r = box_ports.insert(module->name);
+ if (r.second) {
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
IdString carry_in, carry_out;
- for (const auto &port_name : m->ports) {
- auto w = m->wire(port_name);
+ for (const auto &port_name : module->ports) {
+ auto w = module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
- if (w->port_input) {
- if (carry_in != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
+ log_assert(w->port_input != w->port_output);
+ if (w->port_input)
carry_in = port_name;
- }
- if (w->port_output) {
- if (carry_out != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
+ else if (w->port_output)
carry_out = port_name;
- }
}
else
- r2.first->second.push_back(port_name);
+ r.first->second.push_back(port_name);
}
- if (carry_in != IdString() && carry_out == IdString())
- log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
- if (carry_in == IdString() && carry_out != IdString())
- log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
if (carry_in != IdString()) {
- r2.first->second.push_back(carry_in);
- r2.first->second.push_back(carry_out);
+ r.first->second.push_back(carry_in);
+ r.first->second.push_back(carry_out);
+ }
+ }
+
+ std::vector<SigBit> inputs;
+ std::vector<SigBit> outputs;
+ for (auto port_name : r.first->second) {
+ auto wire = module->wire(port_name);
+ if (wire->port_input)
+ for (int i = 0; i < GetSize(wire); i++)
+ inputs.emplace_back(wire, i);
+ if (wire->port_output)
+ for (int i = 0; i < GetSize(wire); i++)
+ outputs.emplace_back(wire, i);
+ }
+
+ ss << log_id(module) << " " << module->attributes.at(ID(abc9_box_id)).as_int();
+ ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+ ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
+
+ bool first = true;
+ ss << "#";
+ for (const auto &i : inputs) {
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ if (GetSize(i.wire) == 1)
+ ss << log_id(i.wire);
+ else
+ ss << log_id(i.wire) << "[" << i.offset << "]";
+ }
+ ss << std::endl;
+
+ auto &t = timing.setup_module(module).comb;
+ if (t.empty())
+ log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
+
+ for (const auto &o : outputs) {
+ first = true;
+ for (const auto &i : inputs) {
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ auto jt = t.find(std::make_pair(i,o));
+ if (jt == t.end())
+ ss << "-";
+ else
+ ss << jt->second;
+ }
+ ss << " # ";
+ if (GetSize(o.wire) == 1)
+ ss << log_id(o.wire);
+ else
+ ss << log_id(o.wire) << "[" << o.offset << "]";
+ ss << std::endl;
+
+ }
+ ss << std::endl;
+ }
+
+ // ABC expects at least one box
+ if (ss.tellp() == 0)
+ ss << "(dummy) 1 0 0 0";
+
+ design->scratchpad_set_string("abc9_ops.box_library", ss.str());
+}
+
+void write_box(RTLIL::Module *module, const std::string &dst) {
+ std::ofstream ofs(dst);
+ log_assert(ofs.is_open());
+ ofs << module->design->scratchpad_get_string("abc9_ops.box_library");
+ ofs.close();
+}
+
+void reintegrate(RTLIL::Module *module)
+{
+ auto design = module->design;
+ log_assert(design);
+
+ map_autoidx = autoidx++;
+
+ RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
+ if (mapped_mod == NULL)
+ log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
+
+ for (auto w : mapped_mod->wires())
+ module->addWire(remap_name(w->name), GetSize(w));
+
+ dict<IdString,std::vector<IdString>> box_ports;
+
+ for (auto m : design->modules()) {
+ if (!m->attributes.count(ID(abc9_box_id)))
+ continue;
+
+ auto r = box_ports.insert(m->name);
+ if (!r.second)
+ continue;
+
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : m->ports) {
+ auto w = m->wire(port_name);
+ log_assert(w);
+ if (w->get_bool_attribute("\\abc9_carry")) {
+ log_assert(w->port_input != w->port_output);
+ if (w->port_input)
+ carry_in = port_name;
+ else if (w->port_output)
+ carry_out = port_name;
}
+ else
+ r.first->second.push_back(port_name);
+ }
+
+ if (carry_in != IdString()) {
+ r.first->second.push_back(carry_in);
+ r.first->second.push_back(carry_out);
}
}
std::vector<Cell*> boxes;
for (auto cell : module->cells().to_vector()) {
+ if (cell->has_keep_attr())
+ continue;
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
module->remove(cell);
else if (cell->attributes.erase("\\abc9_box_seq"))
std::map<IdString, int> cell_stats;
for (auto mapped_cell : mapped_mod->cells())
{
+ // TODO: Speed up toposort -- we care about NOT ordering only
toposort.node(mapped_cell->name);
if (mapped_cell->type == ID($_NOT_)) {
RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
bit_users[a_bit].insert(mapped_cell->name);
- bit_drivers[y_bit].insert(mapped_cell->name);
+ // Ignore inouts for topo ordering
+ if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
+ bit_drivers[y_bit].insert(mapped_cell->name);
if (!a_bit.wire) {
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
// (TODO: Optimise by not cloning unless will increase depth)
RTLIL::IdString driver_name;
if (GetSize(a_bit.wire) == 1)
- driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
+ driver_name = stringf("$lut%s", a_bit.wire->name.c_str());
else
- driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
+ driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset);
driver_lut = mapped_mod->cell(driver_name);
}
if (!driver_lut) {
// If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT
- RTLIL::Cell *cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
+ RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())),
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
}
if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
- // Convert buffer into direct connection
- if (mapped_cell->type == ID($lut) &&
- GetSize(mapped_cell->getPort(ID::A)) == 1 &&
- mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
- SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
- SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
- module->connect(my_y, my_a);
- log_abort();
- continue;
- }
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = mapped_cell->parameters;
cell->attributes = mapped_cell->attributes;
}
if (cell->output(mapped_conn.first))
for (auto i : mapped_conn.second)
- bit_drivers[i].insert(mapped_cell->name);
+ // Ignore inouts for topo ordering
+ if (i.wire && !(i.wire->port_input && i.wire->port_output))
+ bit_drivers[i].insert(mapped_cell->name);
}
}
else {
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
- log_assert(existing_cell);
- log_assert(mapped_cell->type.begins_with("$__boxid"));
+ if (!existing_cell)
+ log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
+
+ if (existing_cell->type == ID($__ABC9_DELAY)) {
+ SigBit I = mapped_cell->getPort(ID(i));
+ SigBit O = mapped_cell->getPort(ID(o));
+ if (I.wire)
+ I.wire = module->wires_.at(remap_name(I.wire->name));
+ log_assert(O.wire);
+ O.wire = module->wires_.at(remap_name(O.wire->name));
+ module->connect(O, I);
+ continue;
+ }
- auto type = box_lookup.at(mapped_cell->type, IdString());
- if (type == IdString())
- log_error("No module with abc9_box_id = %s found.\n", mapped_cell->type.c_str() + strlen("$__boxid"));
- mapped_cell->type = type;
+ RTLIL::Module* box_module = design->module(existing_cell->type);
+ IdString derived_type = box_module->derive(design, existing_cell->parameters);
+ RTLIL::Module* derived_module = design->module(derived_type);
+ log_assert(derived_module);
+ log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
+ mapped_cell->type = existing_cell->type;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = existing_cell->parameters;
cell->attributes = existing_cell->attributes;
module->swap_names(cell, existing_cell);
- auto it = mapped_cell->connections_.find("\\i");
- log_assert(it != mapped_cell->connections_.end());
- SigSpec inputs = std::move(it->second);
- mapped_cell->connections_.erase(it);
- it = mapped_cell->connections_.find("\\o");
- log_assert(it != mapped_cell->connections_.end());
- SigSpec outputs = std::move(it->second);
- mapped_cell->connections_.erase(it);
+ auto jt = mapped_cell->connections_.find("\\i");
+ log_assert(jt != mapped_cell->connections_.end());
+ SigSpec inputs = std::move(jt->second);
+ mapped_cell->connections_.erase(jt);
+ jt = mapped_cell->connections_.find("\\o");
+ log_assert(jt != mapped_cell->connections_.end());
+ SigSpec outputs = std::move(jt->second);
+ mapped_cell->connections_.erase(jt);
- RTLIL::Module* box_module = design->module(mapped_cell->type);
auto abc9_flop = box_module->attributes.count("\\abc9_flop");
if (!abc9_flop) {
for (const auto &i : inputs)
bit_users[i].insert(mapped_cell->name);
for (const auto &i : outputs)
- bit_drivers[i].insert(mapped_cell->name);
+ // Ignore inouts for topo ordering
+ if (i.wire && !(i.wire->port_input && i.wire->port_output))
+ bit_drivers[i].insert(mapped_cell->name);
}
int input_count = 0, output_count = 0;
- for (const auto &port_name : box_ports.at(cell->type)) {
+ for (const auto &port_name : box_ports.at(derived_type)) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
c.wire = module->wires_.at(remap_name(c.wire->name));
newsig.append(c);
}
-
- auto it = existing_cell->connections_.find(port_name);
- if (it == existing_cell->connections_.end())
- continue;
- if (GetSize(newsig) > GetSize(it->second))
- newsig = newsig.extract(0, GetSize(it->second));
- else
- log_assert(GetSize(newsig) == GetSize(it->second));
-
cell->setPort(port_name, newsig);
if (w->port_input && !abc9_flop)
// Stitch in mapped_mod's inputs/outputs into module
for (auto port : mapped_mod->ports) {
- RTLIL::Wire *w = mapped_mod->wire(port);
+ RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
+ if (wire->attributes.erase(ID(abc9_scc_id))) {
+ auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
+ log_assert(r);
+ }
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire));
RTLIL::SigSig conn;
- if (w->port_output) {
+ if (mapped_wire->port_output) {
conn.first = signal;
conn.second = remap_wire;
out_wires++;
module->connect(conn);
}
- else if (w->port_input) {
+ else if (mapped_wire->port_input) {
conn.first = remap_wire;
conn.second = signal;
in_wires++;
}
}
+ // ABC9 will return $_NOT_ gates in its mapping (since they are
+ // treated as being "free"), in particular driving primary
+ // outputs (real primary outputs, or cells treated as blackboxes)
+ // or driving box inputs.
+ // Instead of just mapping those $_NOT_ gates into 2-input $lut-s
+ // at an area and delay cost, see if it is possible to push
+ // this $_NOT_ into the driving LUT, or into all sink LUTs.
+ // When this is not possible, (i.e. this signal drives two primary
+ // outputs, only one of which is complemented) and when the driver
+ // is a LUT, then clone the LUT so that it can be inverted without
+ // increasing depth/delay.
for (auto &it : bit_users)
if (bit_drivers.count(it.first))
for (auto driver_cell : bit_drivers.at(it.first))
log("\n");
log(" abc9_ops [options] [selection]\n");
log("\n");
+ log("This pass contains a set of supporting operations for use during ABC technology\n");
+ log("mapping, and is expected to be called in conjunction with other operations from\n");
+ log("the `abc9' script pass. Only fully-selected modules are supported.\n");
+ log("\n");
+ log(" -check\n");
+ log(" check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
+ log(" (* abc9_carry *) is only given for one input/output port, etc.\n");
+ log("\n");
+ log(" -prep_delays\n");
+ log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
+ log(" certain required times.\n");
+ log("\n");
+ log(" -mark_scc\n");
+ log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n");
+ log(" (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
+ log(" wires driven by this cell's outputs with a (* keep *) attribute in order\n");
+ log(" to break the SCC. this temporary attribute will be removed on -reintegrate.\n");
+ log("\n");
+ log(" -prep_xaiger\n");
+ log(" prepare the design for XAIGER output. this includes computing the\n");
+ log(" topological ordering of ABC9 boxes, as well as preparing the\n");
+ log(" '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
+ log(" whiteboxes.\n");
+ log("\n");
+ log(" -dff\n");
+ log(" consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
+ log(" during -prep_{delays,xaiger,box}.\n");
+ log("\n");
+ log(" -prep_dff\n");
+ log(" compute the clock domain and initial value of each flop in the design.\n");
+ log(" process the '$holes' module to support clock-enable functionality.\n");
+ log("\n");
+ log(" -prep_lut <maxlut>\n");
+ log(" pre-compute the lut library by analysing all modules marked with\n");
+ log(" (* abc9_lut=<area> *).\n");
+ log("\n");
+ log(" -write_lut <dst>\n");
+ log(" write the pre-computed lut library to <dst>.\n");
+ log("\n");
+ log(" -prep_box\n");
+ log(" pre-compute the box library by analysing all modules marked with\n");
+ log(" (* abc9_box *).\n");
+ log("\n");
+ log(" -write_box <dst>\n");
+ log(" write the pre-computed box library to <dst>.\n");
+ log("\n");
+ log(" -reintegrate\n");
+ log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n");
+ log(" by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
+ log(" inputs and outputs.\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
- bool break_scc_mode = false;
- bool unbreak_scc_mode = false;
+ bool check_mode = false;
+ bool prep_delays_mode = false;
+ bool mark_scc_mode = false;
bool prep_dff_mode = false;
- bool prep_holes_mode = false;
+ bool prep_xaiger_mode = false;
+ bool prep_lut_mode = false;
+ bool prep_box_mode = false;
bool reintegrate_mode = false;
bool dff_mode = false;
+ std::string write_lut_dst;
+ int maxlut = 0;
+ std::string write_box_dst;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
- if (arg == "-break_scc") {
- break_scc_mode = true;
+ if (arg == "-check") {
+ check_mode = true;
continue;
}
- if (arg == "-unbreak_scc") {
- unbreak_scc_mode = true;
+ if (arg == "-mark_scc") {
+ mark_scc_mode = true;
continue;
}
if (arg == "-prep_dff") {
prep_dff_mode = true;
continue;
}
- if (arg == "-prep_holes") {
- prep_holes_mode = true;
+ if (arg == "-prep_xaiger") {
+ prep_xaiger_mode = true;
+ continue;
+ }
+ if (arg == "-prep_delays") {
+ prep_delays_mode = true;
+ continue;
+ }
+ if (arg == "-prep_lut" && argidx+1 < args.size()) {
+ prep_lut_mode = true;
+ maxlut = atoi(args[++argidx].c_str());
+ continue;
+ }
+ if (arg == "-maxlut" && argidx+1 < args.size()) {
+ continue;
+ }
+ if (arg == "-write_lut" && argidx+1 < args.size()) {
+ write_lut_dst = args[++argidx];
+ rewrite_filename(write_lut_dst);
+ continue;
+ }
+ if (arg == "-prep_box") {
+ prep_box_mode = true;
+ continue;
+ }
+ if (arg == "-write_box" && argidx+1 < args.size()) {
+ write_box_dst = args[++argidx];
+ rewrite_filename(write_box_dst);
continue;
}
if (arg == "-reintegrate") {
}
extra_args(args, argidx, design);
- if (!(break_scc_mode || unbreak_scc_mode || prep_dff_mode || reintegrate_mode))
- log_cmd_error("At least one of -{,un}break_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
+ if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
+ log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
+
+ if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !prep_box_mode)
+ log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger,box}.\n");
- if (dff_mode && !prep_holes_mode)
- log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
+ if (check_mode)
+ check(design);
+ if (prep_delays_mode)
+ prep_delays(design, dff_mode);
+ if (prep_lut_mode)
+ prep_lut(design, maxlut);
+ if (prep_box_mode)
+ prep_box(design, dff_mode);
for (auto mod : design->selected_modules()) {
if (mod->get_bool_attribute("\\abc9_holes"))
if (!design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
- if (break_scc_mode)
- break_scc(mod);
- if (unbreak_scc_mode)
- unbreak_scc(mod);
+ if (!write_lut_dst.empty())
+ write_lut(mod, write_lut_dst);
+ if (!write_box_dst.empty())
+ write_box(mod, write_box_dst);
+ if (mark_scc_mode)
+ mark_scc(mod);
if (prep_dff_mode)
prep_dff(mod);
- if (prep_holes_mode)
- prep_holes(mod, dff_mode);
+ if (prep_xaiger_mode)
+ prep_xaiger(mod, dff_mode);
if (reintegrate_mode)
reintegrate(mod);
}