abc9_ops: still emit delay table even box has no timing

[yosys.git] / passes / techmap / attrmvcp.cc

diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
index 50eaf61dff46262ece4450327d2dab9f64ce7965..e59aa6518969ecd1d8a33fbff7f19144fdf1999e 100644 (file)
--- a/passes/techmap/attrmvcp.cc
+++ b/passes/techmap/attrmvcp.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct AttrmvcpPass : public Pass {
        AttrmvcpPass() : Pass("attrmvcp", "move or copy attributes from wires to driving cells") { }
-       virtual void help()
+       void help() YS_OVERRIDE
        {
                log("\n");
                log("    attrmvcp [options] [selection]\n");
@@ -53,7 +53,7 @@ struct AttrmvcpPass : public Pass {
                log("        multiple times.\n");
                log("\n");
        }
-       virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
                log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n");
 
@@ -93,6 +93,7 @@ struct AttrmvcpPass : public Pass {
 
                        for (auto cell : module->selected_cells())
                        for (auto &conn : cell->connections())
+                       {
                                if (driven_mode) {
                                        if (cell->input(conn.first))
                                                for (auto bit : sigmap(conn.second))
@@ -102,6 +103,7 @@ struct AttrmvcpPass : public Pass {
                                                for (auto bit : sigmap(conn.second))
                                                        net2cells[bit].insert(cell);
                                }
+                       }
 
                        for (auto wire : module->selected_wires())
                        {