abc9_ops: still emit delay table even box has no timing

[yosys.git] / passes / techmap / dff2dffs.cc

diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index f74001b7793c8227cba5c3c2f5c7891f4bf35136..3fa1ed5cfbc0792e7c36c251cdb994711f86a175 100644 (file)
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -34,11 +34,16 @@ struct Dff2dffsPass : public Pass {
                log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
                log("dff2dffe for SR over CE priority.\n");
                log("\n");
+               log("    -match-init\n");
+               log("        Disallow merging synchronous set/reset that has polarity opposite of the\n");
+               log("        output wire's init attribute (if any).\n");
+               log("\n");
        }
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
                log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
 
+               bool match_init = false;
                size_t argidx;
                for (argidx = 1; argidx < args.size(); argidx++)
                {
@@ -46,6 +51,10 @@ struct Dff2dffsPass : public Pass {
                        //      singleton_mode = true;
                        //      continue;
                        // }
+                       if (args[argidx] == "-match-init") {
+                               match_init = true;
+                               continue;
+                       }
                        break;
                }
                extra_args(args, argidx, design);
@@ -72,11 +81,11 @@ struct Dff2dffsPass : public Pass {
                                if (cell->type != ID($_MUX_))
                                        continue;
 
-                               SigBit bit_a = sigmap(cell->getPort(ID(A)));
-                               SigBit bit_b = sigmap(cell->getPort(ID(B)));
+                               SigBit bit_a = sigmap(cell->getPort(ID::A));
+                               SigBit bit_b = sigmap(cell->getPort(ID::B));
 
                                if (bit_a.wire == nullptr || bit_b.wire == nullptr)
-                                       sr_muxes[sigmap(cell->getPort(ID(Y)))] = cell;
+                                       sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
                        }
 
                        for (auto cell : ff_cells)
@@ -92,13 +101,10 @@ struct Dff2dffsPass : public Pass {
                                        continue;
 
                                Cell *mux_cell = sr_muxes.at(bit_d);
-                               SigBit bit_a = sigmap(mux_cell->getPort(ID(A)));
-                               SigBit bit_b = sigmap(mux_cell->getPort(ID(B)));
+                               SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
+                               SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
                                SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
 
-                               log("  Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
-                                               log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
-
                                SigBit sr_val, sr_sig;
                                bool invert_sr;
                                sr_sig = bit_s;
@@ -113,6 +119,23 @@ struct Dff2dffsPass : public Pass {
                                        invert_sr = false;
                                }
 
+                               if (match_init) {
+                                       SigBit bit_q = cell->getPort(ID(Q));
+                                       if (bit_q.wire) {
+                                               auto it = bit_q.wire->attributes.find(ID(init));
+                                               if (it != bit_q.wire->attributes.end()) {
+                                                       auto init_val = it->second[bit_q.offset];
+                                                       if (init_val == State::S1 && sr_val != State::S1)
+                                                               continue;
+                                                       if (init_val == State::S0 && sr_val != State::S0)
+                                                               continue;
+                                               }
+                                       }
+                               }
+
+                               log("  Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
+                                               log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
+
                                if (sr_val == State::S1) {
                                        if (cell->type == ID($_DFF_N_)) {
                                                if (invert_sr) cell->type = ID($__DFFS_NN1_);