SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim...

[yosys.git] / passes / techmap / extract.cc

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index a960f2bae050178ea837455e5b2c037015abe767..5a7298087755e4ca625a2d1eeee016943772faa8 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -756,7 +756,7 @@ struct ExtractPass : public Pass {
                                        newCell->parameters = cell->parameters;
                                        for (auto &conn : cell->connections) {
                                                RTLIL::SigSpec sig = sigmap(conn.second);
-                                               for (auto &chunk : sig.chunks())
+                                               for (auto &chunk : sig.chunks_rw())
                                                        if (chunk.wire != NULL)
                                                                chunk.wire = newMod->wires.at(chunk.wire->name);
                                                newCell->connections[conn.first] = sig;