ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
{
- SigBit y = sigmap(SigBit(cell->getPort(ID(Y))));
+ SigBit y = sigmap(SigBit(cell->getPort(ID::Y)));
log_assert(driver.count(y) == 0);
driver[y] = cell;
}
pool<SigBit> new_leaves = leaves;
new_leaves.erase(bit);
- if (cell->hasPort(ID(A))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(A)))));
- if (cell->hasPort(ID(B))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(B)))));
- if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C)))));
- if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D)))));
+ for (auto port : {ID::A, ID::B, ID(C), ID(D)}) {
+ if (!cell->hasPort(port))
+ continue;
+ auto bit = sigmap(SigBit(cell->getPort(port)));
+ if (!bit.wire)
+ continue;
+ new_leaves.insert(bit);
+ }
if (GetSize(new_leaves) > maxbreadth)
continue;
void assign_new_driver(SigBit bit, SigBit new_driver)
{
Cell *cell = driver.at(bit);
- if (sigmap(cell->getPort(ID(Y))) == bit) {
- cell->setPort(ID(Y), module->addWire(NEW_ID));
+ if (sigmap(cell->getPort(ID::Y)) == bit) {
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
module->connect(bit, new_driver);
}
}
log(" Created $fa cell %s.\n", log_id(cell));
- cell->setPort(ID(A), f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
- cell->setPort(ID(B), f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
+ cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
+ cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
cell->setPort(ID(X), X);
- cell->setPort(ID(Y), Y);
+ cell->setPort(ID::Y, Y);
facache[fakey] = make_tuple(X, Y, cell);
}
log(" Created $fa cell %s.\n", log_id(cell));
- cell->setPort(ID(A), f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
- cell->setPort(ID(B), f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
+ cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
+ cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID(C), State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
cell->setPort(ID(X), X);
- cell->setPort(ID(Y), Y);
+ cell->setPort(ID::Y, Y);
}
if (func2.at(key).count(xor2_func)) {