log(" of the tristate driver and the 2nd portname is the internal output\n");
log(" buffering the external signal.\n");
log("\n");
+ log(" -ignore <celltype> <portname>[:<portname>]*\n");
+ log(" Skips mapping inputs/outputs that are already connected to given\n");
+ log(" ports of the given cell. Can be used multiple times. This is in\n");
+ log(" addition to the cells specified as mapping targets.\n");
+ log("\n");
log(" -widthparam <param_name>\n");
log(" Use the specified parameter name to set the port width.\n");
log("\n");
{
log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
- std::string inpad_celltype, inpad_portname, inpad_portname2;
- std::string outpad_celltype, outpad_portname, outpad_portname2;
- std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
- std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
- std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
+ std::string inpad_celltype, inpad_portname_o, inpad_portname_pad;
+ std::string outpad_celltype, outpad_portname_i, outpad_portname_pad;
+ std::string inoutpad_celltype, inoutpad_portname_io, inoutpad_portname_pad;
+ std::string toutpad_celltype, toutpad_portname_oe, toutpad_portname_i, toutpad_portname_pad;
+ std::string tinoutpad_celltype, tinoutpad_portname_oe, tinoutpad_portname_o, tinoutpad_portname_i, tinoutpad_portname_pad;
std::string widthparam, nameparam;
+ pool<pair<IdString, IdString>> ignore;
bool flag_bits = false;
size_t argidx;
std::string arg = args[argidx];
if (arg == "-inpad" && argidx+2 < args.size()) {
inpad_celltype = args[++argidx];
- inpad_portname = args[++argidx];
- split_portname_pair(inpad_portname, inpad_portname2);
+ inpad_portname_o = args[++argidx];
+ split_portname_pair(inpad_portname_o, inpad_portname_pad);
continue;
}
if (arg == "-outpad" && argidx+2 < args.size()) {
outpad_celltype = args[++argidx];
- outpad_portname = args[++argidx];
- split_portname_pair(outpad_portname, outpad_portname2);
+ outpad_portname_i = args[++argidx];
+ split_portname_pair(outpad_portname_i, outpad_portname_pad);
continue;
}
if (arg == "-inoutpad" && argidx+2 < args.size()) {
inoutpad_celltype = args[++argidx];
- inoutpad_portname = args[++argidx];
- split_portname_pair(inoutpad_portname, inoutpad_portname2);
+ inoutpad_portname_io = args[++argidx];
+ split_portname_pair(inoutpad_portname_io, inoutpad_portname_pad);
continue;
}
if (arg == "-toutpad" && argidx+2 < args.size()) {
toutpad_celltype = args[++argidx];
- toutpad_portname = args[++argidx];
- split_portname_pair(toutpad_portname, toutpad_portname2);
- split_portname_pair(toutpad_portname2, toutpad_portname3);
+ toutpad_portname_oe = args[++argidx];
+ split_portname_pair(toutpad_portname_oe, toutpad_portname_i);
+ split_portname_pair(toutpad_portname_i, toutpad_portname_pad);
continue;
}
if (arg == "-tinoutpad" && argidx+2 < args.size()) {
tinoutpad_celltype = args[++argidx];
- tinoutpad_portname = args[++argidx];
- split_portname_pair(tinoutpad_portname, tinoutpad_portname2);
- split_portname_pair(tinoutpad_portname2, tinoutpad_portname3);
- split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
+ tinoutpad_portname_oe = args[++argidx];
+ split_portname_pair(tinoutpad_portname_oe, tinoutpad_portname_o);
+ split_portname_pair(tinoutpad_portname_o, tinoutpad_portname_i);
+ split_portname_pair(tinoutpad_portname_i, tinoutpad_portname_pad);
+ continue;
+ }
+ if (arg == "-ignore" && argidx+2 < args.size()) {
+ std::string ignore_celltype = args[++argidx];
+ std::string ignore_portname = args[++argidx];
+ std::string ignore_portname2;
+ while (!ignore_portname.empty()) {
+ split_portname_pair(ignore_portname, ignore_portname2);
+ ignore.insert(make_pair(RTLIL::escape_id(ignore_celltype), RTLIL::escape_id(ignore_portname)));
+
+ ignore_portname = ignore_portname2;
+ }
continue;
}
if (arg == "-widthparam" && argidx+1 < args.size()) {
}
extra_args(args, argidx, design);
+ if (!inpad_portname_pad.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(inpad_celltype), RTLIL::escape_id(inpad_portname_pad)));
+ if (!outpad_portname_pad.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(outpad_celltype), RTLIL::escape_id(outpad_portname_pad)));
+ if (!inoutpad_portname_pad.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(inoutpad_celltype), RTLIL::escape_id(inoutpad_portname_pad)));
+ if (!toutpad_portname_pad.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(toutpad_celltype), RTLIL::escape_id(toutpad_portname_pad)));
+ if (!tinoutpad_portname_pad.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname_pad)));
+
+ for (auto module : design->modules())
+ if (module->get_blackbox_attribute())
+ for (auto wire : module->wires())
+ if (wire->get_bool_attribute("\\iopad_external_pin"))
+ ignore.insert(make_pair(module->name, wire->name));
+
for (auto module : design->selected_modules())
{
- dict<IdString, pool<int>> skip_wires;
pool<SigBit> skip_wire_bits;
- SigMap sigmap(module);
+ dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
for (auto cell : module->cells())
- {
- if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2))))
- skip_wire_bits.insert(bit);
-
- if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2))))
+ for (auto port : cell->connections())
+ if (ignore.count(make_pair(cell->type, port.first)))
+ for (auto bit : port.second)
skip_wire_bits.insert(bit);
- if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2))))
- skip_wire_bits.insert(bit);
-
- if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3))))
- skip_wire_bits.insert(bit);
-
- if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4))))
- skip_wire_bits.insert(bit);
- }
-
if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
{
- dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
- pool<pair<IdString, IdString>> norewrites;
- SigMap rewrites;
+ dict<SigBit, Cell *> tbuf_bits;
+ pool<SigBit> driven_bits;
+ // Gather tristate buffers and always-on drivers.
for (auto cell : module->cells())
- if (cell->type == "$_TBUF_") {
- SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
- tbuf_bits[bit].first = cell->name;
+ if (cell->type == ID($_TBUF_)) {
+ SigBit bit = cell->getPort(ID::Y).as_bit();
+ tbuf_bits[bit] = cell;
+ } else {
+ for (auto port : cell->connections())
+ if (!cell->known() || cell->output(port.first))
+ for (auto bit : port.second)
+ driven_bits.insert(bit);
}
- for (auto cell : module->cells())
- for (auto port : cell->connections())
- for (auto bit : sigmap(port.second))
- if (tbuf_bits.count(bit))
- tbuf_bits.at(bit).second.insert(cell->name);
+ // If a wire is a target of an assignment, it is driven, unless the source is 'z.
+ for (auto &conn : module->connections())
+ for (int i = 0; i < GetSize(conn.first); i++) {
+ SigBit dstbit = conn.first[i];
+ SigBit srcbit = conn.second[i];
+ if (!srcbit.wire && srcbit.data == State::Sz)
+ continue;
+ driven_bits.insert(dstbit);
+ }
for (auto wire : module->selected_wires())
{
if (!wire->port_output)
continue;
+ // Don't handle inout ports if we have no suitable buffer type.
+ if (wire->port_input && tinoutpad_celltype.empty())
+ continue;
+
+ // likewise for output ports.
+ if (!wire->port_input && toutpad_celltype.empty())
+ continue;
+
for (int i = 0; i < GetSize(wire); i++)
{
SigBit wire_bit(wire, i);
- SigBit mapped_wire_bit = sigmap(wire_bit);
+ Cell *tbuf_cell = nullptr;
- if (tbuf_bits.count(mapped_wire_bit) == 0)
+ if (skip_wire_bits.count(wire_bit))
continue;
- if (skip_wire_bits.count(mapped_wire_bit))
- continue;
-
- auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
- Cell *tbuf_cell = module->cell(tbuf_cache.first);
-
- if (tbuf_cell == nullptr)
- continue;
-
- SigBit en_sig = tbuf_cell->getPort("\\E").as_bit();
- SigBit data_sig = tbuf_cell->getPort("\\A").as_bit();
+ if (tbuf_bits.count(wire_bit))
+ tbuf_cell = tbuf_bits.at(wire_bit);
+
+ SigBit en_sig;
+ SigBit data_sig;
+ bool is_driven = driven_bits.count(wire_bit);
+
+ if (tbuf_cell != nullptr) {
+ // Found a tristate buffer — use it.
+ en_sig = tbuf_cell->getPort(ID(E)).as_bit();
+ data_sig = tbuf_cell->getPort(ID::A).as_bit();
+ } else if (is_driven) {
+ // No tristate buffer, but an always-on driver is present.
+ // If this is an inout port, we're creating a tinoutpad
+ // anyway, just with a constant 1 as enable.
+ if (!wire->port_input)
+ continue;
+ en_sig = SigBit(State::S1);
+ data_sig = wire_bit;
+ } else {
+ // No driver on a wire. Create a tristate pad with always-0
+ // enable.
+ en_sig = SigBit(State::S0);
+ data_sig = SigBit(State::Sx);
+ }
- if (wire->port_input && !tinoutpad_celltype.empty())
+ if (wire->port_input)
{
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
- Wire *owire = module->addWire(NEW_ID);
-
- cell->setPort(RTLIL::escape_id(tinoutpad_portname), en_sig);
- cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
- cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
- cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
- cell->attributes["\\keep"] = RTLIL::Const(1);
-
- for (auto cn : tbuf_cache.second) {
- auto c = module->cell(cn);
- if (c == nullptr)
- continue;
- for (auto port : c->connections()) {
- SigSpec sig = port.second;
- bool newsig = false;
- for (auto &bit : sig)
- if (sigmap(bit) == mapped_wire_bit) {
- bit = owire;
- newsig = true;
- }
- if (newsig)
- c->setPort(port.first, sig);
- }
- }
-
-
- module->remove(tbuf_cell);
- skip_wires[wire->name].insert(i);
-
- norewrites.insert(make_pair(cell->name, RTLIL::escape_id(tinoutpad_portname4)));
- rewrites.add(sigmap(wire_bit), owire);
- continue;
- }
- if (!wire->port_input && !toutpad_celltype.empty())
- {
+ cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig);
+ cell->attributes[ID::keep] = RTLIL::Const(1);
+
+ if (tbuf_cell) {
+ module->remove(tbuf_cell);
+ cell->setPort(RTLIL::escape_id(tinoutpad_portname_o), wire_bit);
+ cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig);
+ } else if (is_driven) {
+ cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), wire_bit);
+ } else {
+ cell->setPort(RTLIL::escape_id(tinoutpad_portname_o), wire_bit);
+ cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig);
+ }
+ skip_wire_bits.insert(wire_bit);
+ if (!tinoutpad_portname_pad.empty())
+ rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad));
+ } else {
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
- cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
- cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
- cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
- cell->attributes["\\keep"] = RTLIL::Const(1);
-
- for (auto cn : tbuf_cache.second) {
- auto c = module->cell(cn);
- if (c == nullptr)
- continue;
- for (auto port : c->connections()) {
- SigSpec sig = port.second;
- bool newsig = false;
- for (auto &bit : sig)
- if (sigmap(bit) == mapped_wire_bit) {
- bit = data_sig;
- newsig = true;
- }
- if (newsig)
- c->setPort(port.first, sig);
- }
- }
+ cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig);
+ cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig);
+ cell->attributes[ID::keep] = RTLIL::Const(1);
- module->remove(tbuf_cell);
- skip_wires[wire->name].insert(i);
- continue;
+ if (tbuf_cell) {
+ module->remove(tbuf_cell);
+ module->connect(wire_bit, data_sig);
+ }
+ skip_wire_bits.insert(wire_bit);
+ if (!toutpad_portname_pad.empty())
+ rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(toutpad_portname_pad));
}
}
}
-
- if (GetSize(norewrites))
- {
- for (auto cell : module->cells())
- for (auto port : cell->connections())
- {
- if (norewrites.count(make_pair(cell->name, port.first)))
- continue;
-
- SigSpec orig_sig = sigmap(port.second);
- SigSpec new_sig = rewrites(orig_sig);
-
- if (orig_sig != new_sig)
- cell->setPort(port.first, new_sig);
- }
- }
}
for (auto wire : module->selected_wires())
if (!wire->port_id)
continue;
- std::string celltype, portname, portname2;
+ std::string celltype, portname_int, portname_pad;
pool<int> skip_bit_indices;
- if (skip_wires.count(wire->name)) {
- if (!flag_bits)
- continue;
- skip_bit_indices = skip_wires.at(wire->name);
- }
-
for (int i = 0; i < GetSize(wire); i++)
- if (skip_wire_bits.count(sigmap(SigBit(wire, i))))
+ if (skip_wire_bits.count(SigBit(wire, i)))
skip_bit_indices.insert(i);
if (GetSize(wire) == GetSize(skip_bit_indices))
continue;
}
celltype = inpad_celltype;
- portname = inpad_portname;
- portname2 = inpad_portname2;
+ portname_int = inpad_portname_o;
+ portname_pad = inpad_portname_pad;
} else
if (!wire->port_input && wire->port_output) {
if (outpad_celltype.empty()) {
continue;
}
celltype = outpad_celltype;
- portname = outpad_portname;
- portname2 = outpad_portname2;
+ portname_int = outpad_portname_i;
+ portname_pad = outpad_portname_pad;
} else
if (wire->port_input && wire->port_output) {
if (inoutpad_celltype.empty()) {
continue;
}
celltype = inoutpad_celltype;
- portname = inoutpad_portname;
- portname2 = inoutpad_portname2;
+ portname_int = inoutpad_portname_io;
+ portname_pad = inoutpad_portname_pad;
} else
log_abort();
log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
- RTLIL::Wire *new_wire = NULL;
- if (!portname2.empty()) {
- new_wire = module->addWire(NEW_ID, wire);
- module->swap_names(new_wire, wire);
- wire->attributes.clear();
- }
-
if (flag_bits)
{
for (int i = 0; i < wire->width; i++)
{
- if (skip_bit_indices.count(i)) {
- if (wire->port_output)
- module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
- else
- module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
+ if (skip_bit_indices.count(i))
continue;
- }
+
+ SigBit wire_bit(wire, i);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
- cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
- if (!portname2.empty())
- cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
+ cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
+
+ if (!portname_pad.empty())
+ rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(portname_pad));
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
- cell->attributes["\\keep"] = RTLIL::Const(1);
+ cell->attributes[ID::keep] = RTLIL::Const(1);
}
}
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
- cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
- if (!portname2.empty())
- cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
+ cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
+
+ if (!portname_pad.empty()) {
+ RTLIL::Wire *new_wire = NULL;
+ new_wire = module->addWire(NEW_ID, wire);
+ module->swap_names(new_wire, wire);
+ wire->attributes.clear();
+ cell->setPort(RTLIL::escape_id(portname_pad), RTLIL::SigSpec(new_wire));
+ }
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
- cell->attributes["\\keep"] = RTLIL::Const(1);
+ cell->attributes[ID::keep] = RTLIL::Const(1);
+ }
+
+ if (!rewrite_bits.count(wire)) {
+ wire->port_id = 0;
+ wire->port_input = false;
+ wire->port_output = false;
+ }
+ }
+
+ for (auto &it : rewrite_bits) {
+ RTLIL::Wire *wire = it.first;
+ RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire);
+ module->swap_names(new_wire, wire);
+ wire->attributes.clear();
+ for (int i = 0; i < wire->width; i++)
+ {
+ SigBit wire_bit(wire, i);
+ if (!it.second.count(i)) {
+ if (wire->port_output)
+ module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
+ else
+ module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
+ } else {
+ auto &new_conn = it.second.at(i);
+ new_conn.first->setPort(new_conn.second, RTLIL::SigSpec(new_wire, i));
+ }
+ }
+
+ if (wire->port_output) {
+ auto jt = new_wire->attributes.find(ID(init));
+ // For output ports, move \init attributes from old wire to new wire
+ if (jt != new_wire->attributes.end()) {
+ wire->attributes[ID(init)] = std::move(jt->second);
+ new_wire->attributes.erase(jt);
+ }
}
wire->port_id = 0;
projects / yosys.git / blobdiff