abc9_ops: still emit delay table even box has no timing
[yosys.git] / passes / techmap / shregmap.cc
index 811b40eac3d7e54eef4e7867c090229ab29d5238..be00e50305b3179e184f8f698d801779164cb2f9 100644 (file)
@@ -141,8 +141,21 @@ struct ShregmapWorker
                                if (opts.init || sigbit_init.count(q_bit) == 0)
                                {
                                        auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
-                                       if (!r.second)
+                                       if (!r.second) {
+                                               // Insertion not successful means that d_bit is already
+                                               // connected to another register, thus mark it as a
+                                               // non chain user ...
                                                sigbit_with_non_chain_users.insert(d_bit);
+                                               // ... and clone d_bit into another wire, and use that
+                                               // wire as a different key in the d_bit-to-cell dictionary
+                                               // so that it can be identified as another chain
+                                               // (omitting this common flop)
+                                               // Link: https://github.com/YosysHQ/yosys/pull/1085
+                                               Wire *wire = module->addWire(NEW_ID);
+                                               module->connect(wire, d_bit);
+                                               sigmap.add(wire, d_bit);
+                                               sigbit_chain_next.insert(std::make_pair(wire, cell));
+                                       }
 
                                        sigbit_chain_prev[q_bit] = cell;
                                        continue;
@@ -160,14 +173,14 @@ struct ShregmapWorker
        {
                for (auto it : sigbit_chain_next)
                {
-                       Cell *c1, *c2 = it.second;
-
                        if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
                                goto start_cell;
 
-                       c1 = sigbit_chain_prev.at(it.first, nullptr);
-                       if (c1 != nullptr)
+                       if (sigbit_chain_prev.count(it.first) != 0)
                        {
+                               Cell *c1 = sigbit_chain_prev.at(it.first);
+                               Cell *c2 = it.second;
+
                                if (c1->type != c2->type)
                                        goto start_cell;
 
@@ -177,17 +190,8 @@ struct ShregmapWorker
                                IdString d_port = opts.ffcells.at(c1->type).first;
                                IdString q_port = opts.ffcells.at(c1->type).second;
 
-                               // If the previous cell's D has other non chain users,
-                               // then it is possible that this previous cell could
-                               // be a start of the chain
-                               SigBit d_bit = sigmap(c1->getPort(d_port).as_bit());
-                               if (sigbit_with_non_chain_users.count(d_bit)) {
-                                       c2 = c1;
-                                       goto start_cell;
-                               }
-
                                auto c1_conn = c1->connections();
-                               auto c2_conn = c1->connections();
+                               auto c2_conn = c2->connections();
 
                                c1_conn.erase(d_port);
                                c1_conn.erase(q_port);
@@ -202,7 +206,7 @@ struct ShregmapWorker
                        }
 
                start_cell:
-                       chain_start_cells.insert(c2);
+                       chain_start_cells.insert(it.second);
                }
        }