abc9_ops: still emit delay table even box has no timing

[yosys.git] / passes / techmap / shregmap.cc

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index d472d1275f92be2513a6d3cef13c0599763da78f..be00e50305b3179e184f8f698d801779164cb2f9 100644 (file)
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -140,10 +140,22 @@ struct ShregmapWorker
 
                                if (opts.init || sigbit_init.count(q_bit) == 0)
                                {
-                                       if (sigbit_chain_next.count(d_bit)) {
+                                       auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
+                                       if (!r.second) {
+                                               // Insertion not successful means that d_bit is already
+                                               // connected to another register, thus mark it as a
+                                               // non chain user ...
                                                sigbit_with_non_chain_users.insert(d_bit);
-                                       } else
-                                               sigbit_chain_next[d_bit] = cell;
+                                               // ... and clone d_bit into another wire, and use that
+                                               // wire as a different key in the d_bit-to-cell dictionary
+                                               // so that it can be identified as another chain
+                                               // (omitting this common flop)
+                                               // Link: https://github.com/YosysHQ/yosys/pull/1085
+                                               Wire *wire = module->addWire(NEW_ID);
+                                               module->connect(wire, d_bit);
+                                               sigmap.add(wire, d_bit);
+                                               sigbit_chain_next.insert(std::make_pair(wire, cell));
+                                       }
 
                                        sigbit_chain_prev[q_bit] = cell;
                                        continue;
@@ -179,7 +191,7 @@ struct ShregmapWorker
                                IdString q_port = opts.ffcells.at(c1->type).second;
 
                                auto c1_conn = c1->connections();
-                               auto c2_conn = c1->connections();
+                               auto c2_conn = c2->connections();
 
                                c1_conn.erase(d_port);
                                c1_conn.erase(q_port);