Renamed SIZE() to GetSize() because of name collision on Win32

[yosys.git] / passes / techmap / simplemap.cc

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 1cba343368afa7147f688a44f70fa5f17fa21d61..c3ca29e50b0ed1ec6c621375321f84a03a4a99a5 100644 (file)
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -32,9 +32,9 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
        RTLIL::SigSpec sig_a = cell->getPort("\\A");
        RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
-       sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+       sig_a.extend(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
-       for (int i = 0; i < SIZE(sig_y); i++) {
+       for (int i = 0; i < GetSize(sig_y); i++) {
                RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
                gate->setPort("\\A", sig_a[i]);
                gate->setPort("\\Y", sig_y[i]);
@@ -46,7 +46,7 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
        RTLIL::SigSpec sig_a = cell->getPort("\\A");
        RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
-       sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+       sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
        module->connect(RTLIL::SigSig(sig_y, sig_a));
 }
@@ -57,14 +57,14 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
        RTLIL::SigSpec sig_b = cell->getPort("\\B");
        RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
-       sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
-       sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
+       sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+       sig_b.extend_u0(GetSize(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
 
        if (cell->type == "$xnor")
        {
-               RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
+               RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
 
-               for (int i = 0; i < SIZE(sig_y); i++) {
+               for (int i = 0; i < GetSize(sig_y); i++) {
                        RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
                        gate->setPort("\\A", sig_t[i]);
                        gate->setPort("\\Y", sig_y[i]);
@@ -80,7 +80,7 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
        if (cell->type == "$xnor") gate_type = "$_XOR_";
        log_assert(!gate_type.empty());
 
-       for (int i = 0; i < SIZE(sig_y); i++) {
+       for (int i = 0; i < GetSize(sig_y); i++) {
                RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
                gate->setPort("\\A", sig_a[i]);
                gate->setPort("\\B", sig_b[i]);
@@ -238,7 +238,7 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
        RTLIL::SigSpec sig_b = cell->getPort("\\B");
        RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
-       for (int i = 0; i < SIZE(sig_y); i++) {
+       for (int i = 0; i < GetSize(sig_y); i++) {
                RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
                gate->setPort("\\A", sig_a[i]);
                gate->setPort("\\B", sig_b[i]);