Merge pull request #951 from YosysHQ/clifford/logdebug

[yosys.git] / passes / techmap / techmap.cc

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1a431846034ede0125478fd581c3901866a0ae64..ab0bd3b54f034361ae8cf68083e1fda8bf3ad317 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -72,6 +72,8 @@ struct TechmapWorker
        pool<IdString> flatten_done_list;
        pool<Cell*> flatten_keep_list;
 
+       pool<string> log_msg_cache;
+
        struct TechmapWireData {
                RTLIL::Wire *wire;
                RTLIL::SigSpec value;
@@ -390,6 +392,7 @@ struct TechmapWorker
 
                bool log_continue = false;
                bool did_something = false;
+               LogMakeDebugHdl mkdebug;
 
                SigMap sigmap(module);
 
@@ -547,6 +550,7 @@ struct TechmapWorker
                                                                if (extmapper_name == "wrap") {
                                                                        std::string cmd_string = tpl->attributes.at("\\techmap_wrap").decode_string();
                                                                        log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
+                                                                       mkdebug.on();
                                                                        Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
                                                                        log_continue = true;
                                                                }
@@ -560,11 +564,21 @@ struct TechmapWorker
                                                                goto use_wrapper_tpl;
                                                        }
 
-                                                       log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
+                                                       auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
+                                                       if (!log_msg_cache.count(msg)) {
+                                                               log_msg_cache.insert(msg);
+                                                               log("%s\n", msg.c_str());
+                                                       }
+                                                       log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
                                                }
                                                else
                                                {
-                                                       log("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
+                                                       auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
+                                                       if (!log_msg_cache.count(msg)) {
+                                                               log_msg_cache.insert(msg);
+                                                               log("%s\n", msg.c_str());
+                                                       }
+                                                       log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
 
                                                        if (extmapper_name == "simplemap") {
                                                                if (simplemap_mappers.count(cell->type) == 0)
@@ -662,6 +676,7 @@ struct TechmapWorker
                                                tpl = techmap_cache[key];
                                        } else {
                                                if (parameters.size() != 0) {
+                                                       mkdebug.on();
                                                        derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
                                                        tpl = map->module(derived_name);
                                                        log_continue = true;
@@ -831,6 +846,7 @@ struct TechmapWorker
                                                if (log_continue) {
                                                        log_header(design, "Continuing TECHMAP pass.\n");
                                                        log_continue = false;
+                                                       mkdebug.off();
                                                }
                                                while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
                                        }
@@ -842,6 +858,7 @@ struct TechmapWorker
                                if (log_continue) {
                                        log_header(design, "Continuing TECHMAP pass.\n");
                                        log_continue = false;
+                                       mkdebug.off();
                                }
 
                                if (extern_mode && !in_recursion)
@@ -861,13 +878,18 @@ struct TechmapWorker
                                                module_queue.insert(m);
                                        }
 
-                                       log("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
+                                       log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
                                        cell->type = m_name;
                                        cell->parameters.clear();
                                }
                                else
                                {
-                                       log("%s %s.%s using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(tpl));
+                                       auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
+                                       if (!log_msg_cache.count(msg)) {
+                                               log_msg_cache.insert(msg);
+                                               log("%s\n", msg.c_str());
+                                       }
+                                       log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
                                        techmap_module_worker(design, module, cell, tpl);
                                        cell = NULL;
                                }
@@ -885,6 +907,7 @@ struct TechmapWorker
                if (log_continue) {
                        log_header(design, "Continuing TECHMAP pass.\n");
                        log_continue = false;
+                       mkdebug.off();
                }
 
                return did_something;
@@ -1085,7 +1108,7 @@ struct TechmapPass : public Pass {
                if (map_files.empty()) {
                        std::istringstream f(stdcells_code);
                        Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
-               } else
+               } else {
                        for (auto &fn : map_files)
                                if (fn.substr(0, 1) == "%") {
                                        if (!saved_designs.count(fn.substr(1))) {
@@ -1104,6 +1127,9 @@ struct TechmapPass : public Pass {
                                                log_cmd_error("Can't open map file `%s'\n", fn.c_str());
                                        Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
                                }
+               }
+
+               log_header(design, "Continuing TECHMAP pass.\n");
 
                std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
                for (auto &it : map->modules_) {
@@ -1211,6 +1237,7 @@ struct FlattenPass : public Pass {
                        }
                }
 
+               log_suppressed();
                log("No more expansions possible.\n");
 
                if (top_mod != NULL)