void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
{
- std::vector<RTLIL::SigChunk> chunks = sig;
+ vector<SigChunk> chunks = sig;
for (auto &chunk : chunks)
if (chunk.wire != NULL) {
std::string wire_name = chunk.wire->name.str();
tpl_written_bits.insert(bit);
SigMap port_signal_map;
+ SigSig port_signal_assign;
- for (auto &it : cell->connections()) {
+ for (auto &it : cell->connections())
+ {
RTLIL::IdString portname = it.first;
if (positional_ports.count(portname) > 0)
portname = positional_ports.at(portname);
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
continue;
}
+
+ if (GetSize(it.second) == 0)
+ continue;
+
RTLIL::Wire *w = tpl->wires_.at(portname);
- RTLIL::SigSig c;
+ RTLIL::SigSig c, extra_connect;
+
if (w->port_output && !w->port_input) {
c.first = it.second;
c.second = RTLIL::SigSpec(w);
apply_prefix(cell->name.str(), c.second, module);
+ extra_connect.first = c.second;
+ extra_connect.second = c.first;
} else if (!w->port_output && w->port_input) {
c.first = RTLIL::SigSpec(w);
c.second = it.second;
apply_prefix(cell->name.str(), c.first, module);
+ extra_connect.first = c.first;
+ extra_connect.second = c.second;
} else {
SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
apply_prefix(cell->name.str(), sig_tpl_pf, module);
- for (int i = 0; i < GetSize(sig_tpl); i++) {
+ for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
c.first.append(sig_mod[i]);
c.second.append(sig_tpl_pf[i]);
c.second.append(sig_mod[i]);
}
}
+ extra_connect.first = sig_tpl_pf;
+ extra_connect.second = sig_mod;
}
+
if (c.second.size() > c.first.size())
c.second.remove(c.first.size(), c.second.size() - c.first.size());
+
if (c.second.size() < c.first.size())
c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
+
log_assert(c.first.size() == c.second.size());
- if (flatten_mode) {
+
+ if (flatten_mode)
+ {
// more conservative approach:
// connect internal and external wires
+
if (sigmaps.count(module) == 0)
sigmaps[module].set(module);
+
if (sigmaps.at(module)(c.first).has_const())
log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
+
module->connect(c);
- } else {
+ }
+ else
+ {
// approach that yields nicer outputs:
// replace internal wires that are connected to external wires
- if (w->port_output)
+
+ if (w->port_output && !w->port_input) {
port_signal_map.add(c.second, c.first);
- else
+ } else
+ if (!w->port_output && w->port_input) {
port_signal_map.add(c.first, c.second);
+ } else {
+ module->connect(c);
+ extra_connect = SigSig();
+ }
+
+ for (auto &attr : w->attributes) {
+ if (attr.first == "\\src")
+ continue;
+ module->connect(extra_connect);
+ break;
+ }
}
}
for (auto &it : tpl->cells_)
{
std::string c_name = it.second->name.str();
+ bool techmap_replace_cell = (!flatten_mode) && (c_name == "\\_TECHMAP_REPLACE_");
- if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
+ if (techmap_replace_cell)
c_name = orig_cell_name;
else
apply_prefix(cell->name.str(), c_name);
RTLIL::Cell *c = module->addCell(c_name, it.second);
design->select(module, c);
+ c->set_src_attribute(cell->get_src_attribute());
+
if (!flatten_mode && c->type.substr(0, 2) == "\\$")
c->type = c->type.substr(1);
if (c->type == "$memrd" || c->type == "$memwr" || c->type == "$meminit") {
IdString memid = c->getParam("\\MEMID").decode_string();
- log_assert(memory_renames.count(memid));
+ log_assert(memory_renames.count(memid) != 0);
c->setParam("\\MEMID", Const(memory_renames[memid].str()));
}
+ if (c->type == "$mem") {
+ string memid = c->getParam("\\MEMID").decode_string();
+ apply_prefix(cell->name.str(), memid);
+ c->setParam("\\MEMID", Const(memid));
+ }
+
if (c->attributes.count("\\src"))
c->add_strpool_attribute("\\src", extra_src_attrs);
+
+ if (techmap_replace_cell)
+ for (auto attr : cell->attributes)
+ if (!c->attributes.count(attr.first))
+ c->attributes[attr.first] = attr.second;
}
for (auto &it : tpl->connections()) {
bool mapped_cell = false;
std::string cell_type = cell->type.str();
+
if (in_recursion && cell_type.substr(0, 2) == "\\$")
cell_type = cell_type.substr(1);
extmapper_module = extmapper_design->addModule(m_name);
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
+ extmapper_cell->set_src_attribute(cell->get_src_attribute());
+
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
if (techmap_cache.count(key) > 0) {
tpl = techmap_cache[key];
} else {
- if (cell->parameters.size() != 0) {
+ if (parameters.size() != 0) {
derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
tpl = map->module(derived_name);
log_continue = true;
if (recursive_mode) {
if (log_continue) {
- log_header("Continuing TECHMAP pass.\n");
+ log_header(design, "Continuing TECHMAP pass.\n");
log_continue = false;
}
while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
continue;
if (log_continue) {
- log_header("Continuing TECHMAP pass.\n");
+ log_header(design, "Continuing TECHMAP pass.\n");
log_continue = false;
}
}
if (log_continue) {
- log_header("Continuing TECHMAP pass.\n");
+ log_header(design, "Continuing TECHMAP pass.\n");
log_continue = false;
}
log(" techmap [-map filename] [selection]\n");
log("\n");
log("This pass implements a very simple technology mapper that replaces cells in\n");
- log("the design with implementations given in form of a verilog or ilang source\n");
+ log("the design with implementations given in form of a Verilog or ilang source\n");
log("file.\n");
log("\n");
log(" -map filename\n");
log("\n");
log(" -recursive\n");
log(" instead of the iterative breadth-first algorithm use a recursive\n");
- log(" depth-first algorithm. both methods should yield equivialent results,\n");
+ log(" depth-first algorithm. both methods should yield equivalent results,\n");
log(" but may differ in performance.\n");
log("\n");
log(" -autoproc\n");
log(" as final cell types by this mode.\n");
log("\n");
log(" -D <define>, -I <incdir>\n");
- log(" this options are passed as-is to the verilog frontend for loading the\n");
- log(" map file. Note that the verilog frontend is also called with the\n");
+ log(" this options are passed as-is to the Verilog frontend for loading the\n");
+ log(" map file. Note that the Verilog frontend is also called with the\n");
log(" '-ignore_redef' option set.\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log(" of constant inputs and shorted inputs at this point and import the\n");
log(" constant and connected bits into the map module. All further commands\n");
log(" are executed in this copy. This is a very convenient way of creating\n");
- log(" optimizied specializations of techmap modules without using the special\n");
+ log(" optimized specializations of techmap modules without using the special\n");
log(" parameters described below.\n");
log("\n");
log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
log("constant value.\n");
log("\n");
log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
- log("of the cell that is beeing replaced.\n");
+ log("and attributes of the cell that is being replaced.\n");
log("\n");
log("See 'help extract' for a pass that does the opposite thing.\n");
log("\n");
log("See 'help flatten' for a pass that does flatten the design (which is\n");
- log("esentially techmap but using the design itself as map library).\n");
+ log("essentially techmap but using the design itself as map library).\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
- log_header("Executing TECHMAP pass (map to technology primitives).\n");
+ log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
log_push();
TechmapWorker worker;
std::ifstream f;
rewrite_filename(fn);
f.open(fn.c_str());
+ yosys_input_files.insert(fn);
if (f.fail())
log_cmd_error("Can't open map file `%s'\n", fn.c_str());
Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
log(" flatten [selection]\n");
log("\n");
log("This pass flattens the design by replacing cells by their implementation. This\n");
- log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
+ log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
log("pass is using the current design as mapping library.\n");
log("\n");
- log("Cells and/or modules with the 'keep_hiearchy' attribute set will not be\n");
+ log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
log("flattened by this command.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
- log_header("Executing FLATTEN pass (flatten design).\n");
+ log_header(design, "Executing FLATTEN pass (flatten design).\n");
log_push();
extra_args(args, 1, design);
worker.flatten_do_list.erase(mod->name);
}
} else {
- for (auto mod : vector<Module*>(design->modules()))
+ for (auto mod : vector<Module*>(design->modules())) {
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
+ }
}
log("No more expansions possible.\n");
projects / yosys.git / blobdiff