add slides

[libreriscv.git] / pinmux / pinmux_chennai_2018.tex

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index ee78845d8bfc1288f829e9fee346ef6004f569e8..2b1bd553706a0dd0b454804ac861645e6e10c32f 100644 (file)
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -3,7 +3,7 @@
 \usepackage{graphics}
 \usepackage{pstricks}
 
-\title{SIMD}
+\title{Pin Multiplexer}
 \author{Rishabh Jain}
 \author{Luke Kenneth Casson Leighton}
 
@@ -103,24 +103,65 @@
                   auto-generated\vspace{30pt}
        }
        \\
-       (translation: it would be insanely costly to do them by hand)
+       (i.e. it would be insanely costly to do them by hand)
   \end{center}
   
 }
 
+\frame{\frametitle{Reduce workload, reduce duplication, reduce risk and cost}
+
+ \begin{itemize}
+   \item Auto-generate everything: documentation, code, libraries etc.
+            \vspace{10pt}
+   \item Standardise: similar to PLIC, propose GPIO and Pinmux
+            \vspace{10pt}
+   \item Standardise format of configuration registers
+                \vspace{10pt}
+   \item Add support for multiple code formats: Chisel3 (SiFive IOF),
+            BSV (Bluespec), Verilog, VHDL, MyHDL.
+                \vspace{10pt}
+   \item Multiple auto-generated code-formats permits cross-validation:\\
+            auto-generated test suite in one HDL can validate a muxer
+            generated for a different target HDL.
+                \vspace{10pt}
+  \end{itemize}
+}
+
 \frame{\frametitle{Muxer cases to handle}
 
  \begin{itemize}
    \item Many FN outputs to Many Pins: no problem\\
-            (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
+            (weird configuration by end-user, but no damage to ASIC)\vspace{6pt}
    \item One Pin to Many FN inputs: no problem\\
-         (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
+         (weird configuration by end-user, but no damage to ASIC)\vspace{6pt}
    \item Many Pins to One FN input: {\bf Priority Mux needed}\\
-            No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{10pt}
+            No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{6pt}
    \item Some FNs (I2C\_SDA, SD\_D0..3) are I/O Buses\\
             Bi-directional control of the Pin must be handed to the
-            FN\vspace{10pt}
-   \item Nice to have: Bus sets pintype, signal strength etc.\vspace{10pt}
+            FN\vspace{6pt}
+   \item Nice to have: Bus sets pintype, signal strength etc.\\
+            e.g. selecting SD/MMC doesn't need manual pin-config.\\
+            \bf{caveat: get that wrong and the ASIC can't be sold}
+  \end{itemize}
+}
+
+
+\frame{\frametitle{Pin Configuration, input and output}
+
+ In/out:
+ \begin{itemize}
+   \item Output-Enable (aka Input disable): switches pad to In or Out
+   \item Output (actually an input wire controlling pin's level, HI/LO)
+   \item Input (actually an output wire set based on pin's driven level)
+ \end{itemize}
+ Characteristics:
+ \begin{itemize}
+   \item Output current level: 10mA / 20mA / 30mA / 40mA
+   \item Input hysteresis: low / middle / high. Stops signal noise
+   \item Pin characteristics: CMOS Push-Push / Open-Drain
+   \item Pull-up enable: built-in 10k (50k?) resistor
+   \item Pull-down enable: built-in 10k (50k?) resistor
+   \item Muxing and IRQ Edge-detection not part of the I/O pin
   \end{itemize}
 }