}
+\frame{\frametitle{Reduce workload, reduce duplication, reduce risk and cost}
+
+ \begin{itemize}
+ \item Auto-generate everything: documentation, code, libraries etc.
+ \vspace{10pt}
+ \item Standardise: similar to PLIC, propose GPIO and Pinmux
+ \vspace{10pt}
+ \item Standardise format of configuration registers
+ \vspace{10pt}
+ \item Add support for multiple code formats: Chisel3 (SiFive IOF),
+ BSV (Bluespec), Verilog, VHDL, MyHDL.
+ \vspace{10pt}
+ \item Multiple auto-generated code-formats permits cross-validation:\\
+ different areas of expertise bootstraps others
+ \vspace{10pt}
+
+ \end{itemize}
+}
+
\frame{\frametitle{Muxer cases to handle}
\begin{itemize}
\item Many FN outputs to Many Pins: no problem\\
- (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
+ (weird configuration by end-user, but no damage to ASIC)\vspace{6pt}
\item One Pin to Many FN inputs: no problem\\
- (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
+ (weird configuration by end-user, but no damage to ASIC)\vspace{6pt}
\item Many Pins to One FN input: {\bf Priority Mux needed}\\
- No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{10pt}
+ No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{6pt}
\item Some FNs (I2C\_SDA, SD\_D0..3) are I/O Buses\\
Bi-directional control of the Pin must be handed to the
- FN\vspace{10pt}
- \item Nice to have: Bus sets pintype, signal strength etc.\vspace{10pt}
+ FN\vspace{6pt}
+ \item Nice to have: Bus sets pintype, signal strength etc.\\
+ e.g. selecting SD/MMC doesn't need manual pin-config.\\
+ \bf{caveat: get that wrong and the ASIC can't be sold}
\end{itemize}
}