add summary slide

[libreriscv.git] / pinmux / pinmux_chennai_2018.tex

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index 8e27f1377193e95b6e4b5c454c9c565e711b3718..9884864ab973fe074beba477f716a23042666c2d 100644 (file)
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -78,8 +78,8 @@
 \frame{\frametitle{Associated Extras}
 
  \begin{itemize}
-   \item Design Specification
-   \item Scenario analysis (whether the chip will fit "markets")
+   \item Design Specification (what markets to target)
+   \item Scenario analysis ({\bf whether} the chip will fit "markets")
    \item Documentation: Summary sheet, Technical Reference Manual.
    \item Test suites
    \item Control Interface (AXI4 / Wishbone / TileLink / other)
@@ -96,6 +96,18 @@
 }
 
 
+\frame{\frametitle{Example: 7 banks, 4-way mux, 160 pins}
+ \begin{center}
+  \includegraphics[height=1.7in]{example_pinmux.jpg}
+ \end{center}
+ \begin{itemize}
+   \item { \bf 17,500 lines of auto-generated HDL (and climbing)}
+   \item { \bf 12,500 lines of auto-generated Summary/Analysis}
+   \item Technical Reference Manual expected to be 100+ pages
+ \end{itemize}
+}
+
+
 \frame{
   \vspace{30pt}
   \begin{center}
@@ -156,18 +168,6 @@
 
 
 
-\frame{\frametitle{Example: 7 banks, 4-way mux, 160 pins}
- \begin{center}
-  \includegraphics[height=1.7in]{example_pinmux.jpg}
- \end{center}
- \begin{itemize}
-   \item { \bf 17,500 lines of auto-generated HDL (and climbing)}
-   \item { \bf 12,500 lines of auto-generated Summary/Analysis}
-   \item Technical Reference Manual expected to be 100+ pages
- \end{itemize}
-}
-
-
 \frame{\frametitle{Muxer cases to handle (One/Many to One/Many) etc.}
 
  \begin{itemize}
@@ -329,7 +329,7 @@
    \item GPIO FN's input muxer is nothing more than an AND gate\\
          (you never route more than one pin to one GPIO)
             \vspace{6pt}
-   \item Any other FN with only 1:1 In also an AND gate \\
+   \item Any other FN with only 1:1 on its IN also just an AND gate \\
             (this just always happens to be true for GPIO)
             \vspace{6pt}
    \item Not all FNs have input capability: clearly they will not
@@ -341,19 +341,17 @@
 \frame{\frametitle{Summary}
 
  \begin{itemize}
+   \item Value of Libre/Open pimux dramatically underestimated\\
+            (and does not presently exist: SiFive IOF not suitable as-is)
+   \item {\bf Only current option: license a commercial Pinmux }
    \item Actual muxing, like SRAM cells, is deceptively simple
-            \vspace{10pt}
    \item Actual pinmuxes are enormous: auto-generation essential
-            \vspace{10pt}
    \item HDLs completely unsuited to auto-generation task\\
-            (TRM, docs): { \bf Modern OO language features needed}
-            \vspace{10pt}
-   \item Verification and auto-generation of different HDLs far
-            easier in a Modern OO language
-            \vspace{10pt}
+            (TRM, docs): {\bf Modern OO language features needed}
+   \item Scenario Analysis / Verification and auto-generation of
+            different HDLs far easier in a Modern OO language
    \item Standardisation for RISC-V saves implementors from huge
             duplication cost (HDL, firmware, docs, maintenance)
-            \vspace{10pt}
    \item { \bf Ultimately it's about saving money and reducing risk }
   \end{itemize}
 }