\vspace{32pt}
\Large{Auto-generating documentation, code \\
and resources for a Pinmux}\\
+ \vspace{16pt}
+ \Large{Saving time and money for SoC / EC designers\\
+ in the RISC-V Ecosystem and beyond}\\
\vspace{24pt}
\Large{[proposed for] Chennai 9th RISC-V Workshop}\\
\vspace{16pt}
\item Pin: an I/O pad. May be driven (input) or may drive (output).
\item FN: term for a single-wire "function", such as UART\_TX,
I2C\_SDA, SDMMC\_D0 etc. may be an input, output or both
- (bi-directional case: two wires are always allocated, one
+ (bi-directional case: two wires are {\bf always} allocated, one
for input to the function and one for output from the function).
\item Bus: a group of bi-directional functions (SDMMC D0 to D3)
- where the direction is ganged and under the Bus's control
+ where the direction is ganged and {\bf under the Bus's control}
\item Input Priority Muxer: a multiplexer with N selector
wires and N associated inputs. The lowest (highest?) indexed
"selector" enabled results in its
input being routed to the output.
- \item Output Demuxer: a one-to-many "redirector" where a single
- input is "routed" to any one output, based
- on a selector.
+ \item Output Muxer: a many-to-one "redirector" where any one
+ output "routed" to the input, based on a selector "address".
\end{itemize}
}
\frame{\frametitle{Associated Extras}
\begin{itemize}
- \item Design Specification
- \item Scenario analysis (whether the chip will fit "markets")
+ \item Design Specification (what markets to target)
+ \item Scenario analysis ({\bf whether} the chip will fit "markets")
\item Documentation: Summary sheet, Technical Reference Manual.
\item Test suites
\item Control Interface (AXI4 / Wishbone / TileLink / other)
}
+\frame{\frametitle{Example: 7 banks, 4-way mux, 160 pins}
+ \begin{center}
+ \includegraphics[height=1.7in]{example_pinmux.jpg}
+ \end{center}
+ \begin{itemize}
+ \item { \bf 17,500 lines of auto-generated HDL (and climbing)}
+ \item { \bf 12,500 lines of auto-generated Summary/Analysis}
+ \item Technical Reference Manual expected to be 100+ pages
+ \end{itemize}
+}
+
+
\frame{
\vspace{30pt}
\begin{center}
\begin{itemize}
\item Auto-generate everything: documentation, code, libraries etc.
\vspace{10pt}
- \item Standardise: similar to PLIC, propose GPIO and Pinmux
+ \item Standardise: similar to PLIC, propose GPIO and Pinmux\\
+ saves engineering effort, design effort and much more
\vspace{10pt}
\item Standardise format of configuration registers:
saves code duplication effort (multiple software environments)
{ \bf (before spending money on hardware engineers!) }
\vspace{4pt}
\item Scenarios represent target markets: ICs to be connected\\
- (GPS, NAND IC, WIFI etc. May require preliminary schematics
+ (GPS, NAND IC, WIFI etc. May require draft schematics
drawn up, or client-supplied schematics analysed).
\vspace{4pt}
\item Analyse the scenarios: if pins are missing, alter and repeat.\\
\vspace{4pt}
\item Eventually the pinmux meets all requirements...\\
- { \bf without spending USD \$5m to \$50m to find out }
+ { \bf without spending USD \$5-50m to find out it doesn't!}
\end{itemize}
}
+
\frame{\frametitle{Muxer cases to handle (One/Many to One/Many) etc.}
\begin{itemize}
\item Pull-up enable: built-in 10k (50k?) resistor
\item Pull-down enable: built-in 10k (50k?) resistor
\item Muxing and IRQ Edge-detection not part of the I/O pin
+ \item Other? (impedance? not normally part of commercial pinmux)
\end{itemize}
}
}
+\frame{\frametitle{GPIO (only): Simplified I/O pad Diagram (FN only)}
+ \begin{center}
+ \includegraphics[height=2.5in]{reg_gpio_pinblock.jpg}\\
+ {\bf 3 wires: IN, OUT, OUTEN (also = !INEN) }
+ \end{center}
+}
+
+
+\frame{\frametitle{Output Muxer (very simple)}
+ \begin{center}
+ \includegraphics[height=1.1in]{reg_gpio_out_mux.jpg}\\
+ {\bf Ouput Muxer using 2-bit address selection}\\
+ \end{center}
+ \begin{itemize}
+ \item Very straightforward (deceptively so, like SRAM cells)
+ \item Used in both OUT routing and Direction-control routing\\
+ (same address for each, connected to same FNs)
+ \item More complex pinmux will have 3-bit addressing (8 FNs)\\
+ (Note: not all outputs will be connected, depends on pinmux)
+ \end{itemize}
+}
+
+
\frame{\frametitle{In/Out muxing, direction control: GPIO just a FN}
\begin{center}
\includegraphics[height=2.5in]{reg_gpio_fn_ctrl.jpg}\\
- {\bf Note: function can control I/O direction}
+ {\bf Note: function can control I/O direction (bus)}
\end{center}
}
-\frame{\frametitle{GPIO (only): Simplified I/O pad Diagram (FN only)}
+\frame{\frametitle{Direction Control: Function not bi-directional (bus)}
\begin{center}
- \includegraphics[height=2.5in]{reg_gpio_pinblock.jpg}\\
- {\bf 3 wires: IN, OUT, OUTEN (also = !INEN) }
+ \includegraphics[height=2.5in]{reg_gpio_fn_ctrl2.jpg}\\
+ Note: Function {\bf does not} control I/O direction
\end{center}
}
}
-\frame{\frametitle{Input Mux Wiring}
+\frame{\frametitle{Input Priority-Mux Wiring: very different from Out-Mux}
\begin{center}
\includegraphics[height=2.5in]{reg_gpio_in_wiring.jpg}\\
{\bf Pin Mux selection vals NOT same as FN selection vals}
}
+\frame{\frametitle{Input Priority-Mux Wiring}
+
+ \begin{itemize}
+ \item In-Muxer selection number (0,1,2,3) obviously has to match
+ with Out-Muxer order (otherwise a bi-directional FN
+ needs different Mux-register settings for
+ selecting either IN or OUT)
+ \vspace{6pt}
+ \item Priority-mux selection values do not actually matter,
+ and have nothing to do with the actual Muxer settings.
+ \vspace{6pt}
+ \item GPIO FN's input muxer is nothing more than an AND gate\\
+ (you never route more than one pin to one GPIO)
+ \vspace{6pt}
+ \item Any other FN with only 1:1 on its IN also just an AND gate \\
+ (this just always happens to be true for GPIO)
+ \vspace{6pt}
+ \item Not all FNs have input capability: clearly they will not
+ be included in the In-Muxing.
+ \end{itemize}
+}
+
+
\frame{\frametitle{Summary}
\begin{itemize}
- \item TODO
+ \item Value of Libre/Open pimux dramatically underestimated\\
+ (and does not presently exist: SiFive IOF not suitable as-is)
+ \item {\bf Only current option: license a commercial Pinmux }
+ \item Actual muxing, like SRAM cells, is deceptively simple
+ \item Actual pinmuxes are enormous: auto-generation essential
+ \item HDLs completely unsuited to auto-generation task\\
+ (TRM, docs): {\bf Modern OO language features needed}
+ \item Scenario Analysis / Verification and auto-generation of
+ different HDLs far easier in a Modern OO language
+ \item Standardisation for RISC-V saves implementors from huge
+ duplication cost (HDL, firmware, docs, maintenance)
+ \item { \bf Ultimately it's about saving money and reducing risk }
\end{itemize}
}
projects / libreriscv.git / blobdiff