}
+\frame{\frametitle{What options are available (at time of writing)? [1]}
+
+ \vspace{6pt}
+ {\bf Commercial licensed}:
+ \vspace{4pt}
+ \begin{itemize}
+ \item Cost: unknown.
+ \item Flexibility: unknown.
+ \item Language: unknown.
+ \item Capability for auto-generation of Docs: unknown.
+ \item Capability for auto-generation of ancillary resources: unknown.
+ \item Suitability for wide range of systems: unknown.
+ \vspace{10pt}
+ \item Suitability for saving RISC-V ecosystem money: {\bf NONE }
+ \item Suitability for collaboration: {\bf ZERO} (i.e. don't bother)
+ \end{itemize}
+}
+
+
+\frame{\frametitle{What options are available (at time of writing)? [2]}
+
+ \vspace{6pt}
+ {\bf SiFive IOF (Freedom E310, Unleashed U540)}:
+ \vspace{4pt}
+ \begin{itemize}
+ \item License: Good!
+ \item Flexibility: not so good.
+ \item Language: chisel3.
+ \item Capability for auto-generation of Docs: none.
+ \item Capability for auto-generation of ancillary resources: partial.
+ \item Suitability for wide range of systems: not so good.
+ \vspace{10pt}
+ \item Suitability for saving RISC-V ecosystem money: {\bf Low }\\
+ \item Suitability for collaboration: {\bf GOOD} (but: written in Chisel3)
+ \end{itemize}
+}
+
+
+\frame{\frametitle{What options are available (at time of writing)? [3]}
+
+ \vspace{10pt}
+ \begin{center}
+ {\Huge
+ None. No suitable\vspace{20pt}\\
+ Libre-licensed\vspace{20pt}\\
+ pinmux exists\vspace{20pt}
+ }
+ \\
+ (which is really weird, given how there's so many libre UART,
+ SPI and other peripheral libraries, even libre-licensed PCIe and
+ SATA PHYs and even USB3 Pipe, hence the reason for this initiative)
+ \end{center}
+
+}
+
+
\frame{\frametitle{Associated Extras}
\begin{itemize}
- \item Design Specification
- \item Scenario analysis (whether the chip will fit "markets")
+ \item Design Specification (what markets to target)
+ \item Scenario analysis ({\bf whether} the chip will fit "markets")
\item Documentation: Summary sheet, Technical Reference Manual.
\item Test suites
\item Control Interface (AXI4 / Wishbone / TileLink / other)
}
+
+\frame{\frametitle{Example: 7 banks, 4-way mux, 160 pins}
+ \begin{center}
+ \includegraphics[height=1.5in]{example_pinmux.jpg}\\
+ 7 "banks" with separate VCC. Each no more than 32 bits
+ \end{center}
+ \begin{itemize}
+ \item { \bf 17,500 lines of auto-generated HDL (and climbing)}
+ \item { \bf 12,500 lines of auto-generated Summary/Analysis}
+ \item Technical Reference Manual expected to be 100+ pages
+ \end{itemize}
+}
+
+
\frame{\frametitle{Reduce workload, reduce duplication, reduce risk and cost}
\begin{itemize}
\frame{\frametitle{Design Spec and Scenario Analysis}
\begin{itemize}
- \item Analyse the target markets that the chip will sell in\\
+ \item Analyse the target markets (scenarios) that the chip will sell in\\
(multiple markets increases sales volume, reduces chip cost)
\vspace{4pt}
+ \item Scenarios represent target markets: ICs to be connected\\
+ (GPS, NAND IC, WIFI etc. May require prototype schematics
+ drawn up, or client-supplied schematics analysed).
+ \vspace{4pt}
\item Create a formal (python-based) specification for the pinmux
\vspace{4pt}
- \item Add scenarios then check that they meet the requirements\\
+ \item Add scenarios (in python), check that they meet requirements\\
{ \bf (before spending money on hardware engineers!) }
\vspace{4pt}
- \item Scenarios represent target markets: ICs to be connected\\
- (GPS, NAND IC, WIFI etc. May require draft schematics
- drawn up, or client-supplied schematics analysed).
- \vspace{4pt}
\item Analyse the scenarios: if pins are missing, alter and repeat.\\
\vspace{4pt}
\item Eventually the pinmux meets all requirements...\\
}
+
\frame{\frametitle{Muxer cases to handle (One/Many to One/Many) etc.}
\begin{itemize}
\item Pull-up enable: built-in 10k (50k?) resistor
\item Pull-down enable: built-in 10k (50k?) resistor
\item Muxing and IRQ Edge-detection not part of the I/O pin
+ \item Other? (impedance? not normally part of commercial pinmux)
\end{itemize}
}
}
+\frame{\frametitle{Output Muxer (very simple)}
+ \begin{center}
+ \includegraphics[height=1.1in]{reg_gpio_out_mux.jpg}\\
+ {\bf Ouput Muxer using 2-bit address selection}\\
+ \end{center}
+ \begin{itemize}
+ \item Very straightforward (deceptively so, like SRAM cells)
+ \item Used in both OUT routing and Direction-control routing\\
+ (same address for each, connected to same FNs)
+ \item More complex pinmux will have 3-bit addressing (8 FNs)\\
+ (Note: not all outputs will be connected, depends on pinmux)
+ \end{itemize}
+}
+
+
\frame{\frametitle{In/Out muxing, direction control: GPIO just a FN}
\begin{center}
\includegraphics[height=2.5in]{reg_gpio_fn_ctrl.jpg}\\
\item GPIO FN's input muxer is nothing more than an AND gate\\
(you never route more than one pin to one GPIO)
\vspace{6pt}
- \item Any other FN with only 1:1 In also an AND gate \\
+ \item Any other FN with only 1:1 on its IN also just an AND gate \\
(this just always happens to be true for GPIO)
\vspace{6pt}
\item Not all FNs have input capability: clearly they will not
\frame{\frametitle{Summary}
\begin{itemize}
- \item TODO
+ \item Value of Libre/Open pimux dramatically underestimated\\
+ (and does not presently exist: SiFive's IOF not suitable as-is)\\
+ {\bf Only current option: license a commercial Pinmux }
+ \item Actual muxing (like SRAM cells) is deceptively simple
+ \item Actual pinmuxes are enormous: auto-generation essential
+ \item HDLs completely unsuited to auto-generation task\\
+ (TRM, docs): {\bf Modern OO language needed i.e. python}
+ \item Scenario Analysis / Verification and auto-generation of
+ different HDLs far easier in a Modern OO language\\
+ (better libraries, more developers)
+ \item Standardisation for RISC-V saves implementors from huge
+ duplication cost (HDL, firmware, docs, maintenance)
+ \item { \bf Ultimately it's about saving money and reducing risk }
\end{itemize}
}
projects / libreriscv.git / blobdiff