add slides

[libreriscv.git] / pinmux / pinmux_chennai_2018.tex

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index a9ab96450686f7615b5092478110256231426d91..c11dc223d48ebc9df3f9825b7bbdce362b966247 100644 (file)
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -108,18 +108,40 @@
   
 }
 
-\frame{\frametitle{Muxer cases to handle}
+\frame{\frametitle{Reduce workload, reduce duplication, reduce risk and cost}
 
  \begin{itemize}
-   \item Many FN outputs to Many Pins: no problem\\
-            (weird configuration by end-user, but no damage to ASIC)\vspace{6pt}
+   \item Auto-generate everything: documentation, code, libraries etc.
+            \vspace{10pt}
+   \item Standardise: similar to PLIC, propose GPIO and Pinmux
+            \vspace{10pt}
+   \item Standardise format of configuration registers:
+            saves code duplication effort (multiple software environments)
+                \vspace{10pt}
+   \item Add support for multiple code formats: Chisel3 (SiFive IOF),
+            BSV (Bluespec), Verilog, VHDL, MyHDL.
+                \vspace{10pt}
+   \item Multiple auto-generated code-formats permits cross-validation:\\
+            auto-generated test suite in one HDL can validate a muxer
+            generated for a different target HDL.
+                \vspace{10pt}
+  \end{itemize}
+}
+
+\frame{\frametitle{Muxer cases to handle (One/Many to One/Many) etc.}
+
+ \begin{itemize}
+   \item One FN outputs to Many Pins: no problem\\
+            (weird configuration by end-user, but no damage to ASIC)
    \item One Pin to Many FN inputs: no problem\\
-         (weird configuration by end-user, but no damage to ASIC)\vspace{6pt}
+         (weird configuration by end-user, but no damage to ASIC)
    \item Many Pins to One FN input: {\bf Priority Mux needed}\\
-            No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{6pt}
+            No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged
+   \item Many FN outputs simultaneously to one Pin: {\bf does not occur}\\
+            (not desirable and not possible, as part of the pinmux design)
    \item Some FNs (I2C\_SDA, SD\_D0..3) are I/O Buses\\
             Bi-directional control of the Pin must be handed to the
-            FN\vspace{6pt}
+            FN
    \item Nice to have: Bus sets pintype, signal strength etc.\\
             e.g. selecting SD/MMC doesn't need manual pin-config.\\
             \bf{caveat: get that wrong and the ASIC can't be sold}
@@ -129,13 +151,13 @@
 
 \frame{\frametitle{Pin Configuration, input and output}
 
- In/out:
+ In/out: {\bf Note: these all require multiplexing }
  \begin{itemize}
    \item Output-Enable (aka Input disable): switches pad to In or Out
    \item Output (actually an input wire controlling pin's level, HI/LO)
    \item Input (actually an output wire set based on pin's driven level)
  \end{itemize}
- Characteristics:
+ Characteristics: {\bf Note: these do not require multiplexing }
  \begin{itemize}
    \item Output current level: 10mA / 20mA / 30mA / 40mA
    \item Input hysteresis: low / middle / high. Stops signal noise
@@ -154,6 +176,29 @@
  \end{center}
 }
 
+\frame{\frametitle{Pin Configuration, input and output}
+
+ \begin{itemize}
+   \item Standard Mux design {\bf cannot deal with many-to-one inputs}\\
+            (SiFive IOF source code from Freedom U310 cannot, either)
+            \vspace{4pt}
+   \item I/O pad configuration conflated with Muxer conflated with GPIO
+         conflated with EINT
+                    \vspace{4pt}
+ \end{itemize}
+   {\bf IMPORTANT to separate all of these out:
+                    \vspace{4pt}}
+ \begin{itemize}
+   \item EINTs to be totally separate FNs. managed by RISC-V PLIC\\
+         (If every GPIO was an EINT it would mean 100+ IRQs)
+                    \vspace{4pt}
+   \item GPIO In/Out/Direction treated just like any other FN\\
+            (but happen to have AXI4 memory-mapping)
+                    \vspace{4pt}
+   \item Pad configuration separated and given one-to-one Registers\\
+            (SRAMs set by AXI4 to control mux, pullup, current etc.)
+ \end{itemize}
+}
 
 \frame{\frametitle{Register-to-pad "control" settings}
  \begin{center}