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[libreriscv.git] / pinmux / pinmux_chennai_2018.tex

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index 0175cbd88d6c79d3a123744606a1d57e29b3d486..e866254a15f07acfe4cd489c796b13fd18d49730 100644 (file)
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -43,8 +43,28 @@
    \item Input Priority Muxer: a multiplexer that has N selector
                 wires and N inputs, where the lowest (or highest) indexed
                 "selector" that is enabled results in its corresponding
-                input being routed to the output.\vspace{10pt}
-   \item TODO\vspace{10pt}
+                input being routed to the output.
+   \item Output Demuxer: a one-to-many "redirector" where a single
+            input is "routed" to any one of a number of outputs, based
+            on a selection address.
+   \item GPIO: general-purpose reconfigureable I/O (Input/Output).
+  \end{itemize}
+}
+
+
+\frame{\frametitle{Why, How and What is a Pinmux?}
+
+ \begin{itemize}
+   \item Why? To save cost, increase yield, and to target multiple
+         markets with the same design, thereby increasing uptake
+         and consequently taking advantage of volume pricing.\vspace{10pt}
+         \\
+         Summary: it's all about making more money!\vspace{10pt}
+   \item How? By multiplexing many more functions (100 to 1,200) than there
+         are actual available pins (48 to 500), the required chip package
+            is far less costly and the chip more desirable\vspace{10pt}
+   \item What? A many-to-many dynamically-configureable router of
+         I/O functions to I/O pins\vspace{10pt}
   \end{itemize}
 }
 
@@ -56,7 +76,7 @@
             (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
    \item One Pin to Many FN inputs: no problem\\
          (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
-   \item Many Pins to One FN input {\bf Priority Mux needed}\\
+   \item Many Pins to One FN input: {\bf Priority Mux needed}\\
             No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{10pt}
    \item Some FNs (I2C\_SDA, SD\_D0..3) are I/O Buses\\
             Bi-directional control of the Pin must be handed to the