""" Example 5: Making use of PyRTL and Introspection. """
from copy import deepcopy
-from migen import *
+from migen import Module, Signal
from migen.fhdl import verilog
+from migen.fhdl.bitcontainer import value_bits_sign
# The following example shows how pyrtl can be used to make some interesting
self._current_stage_num = 0
def _setup(self):
- stage_list = [method for method in dir(self) if method.startswith('stage')]
+ stage_list = []
+ for method in dir(self):
+ if method.startswith('stage'):
+ stage_list.append(method)
for stage in sorted(stage_list):
stage_method = getattr(self, stage)
stage_method()
next_stage = self._current_stage_num + 1
pipereg_id = str(self._current_stage_num) + 'to' + str(next_stage)
rname = 'pipereg_' + pipereg_id + '_' + name
- #new_pipereg = pyrtl.Register(bitwidth=len(value), name=rname)
- new_pipereg = Signal(len(value), name_override=rname)
+ new_pipereg = Signal(value_bits_sign(value), name_override=rname)
if next_stage not in self._pipeline_register_map:
self._pipeline_register_map[next_stage] = {}
self._pipeline_register_map[next_stage][name] = new_pipereg
def __init__(self, pipe):
super(SimplePipelineExample, self).__init__(pipe)
- self._loopback = Signal()
+ self._loopback = Signal(4)
self._setup()
def stage0(self):
- n = Signal()
self.n = ~self._loopback
def stage1(self):
- self.n = self.n
+ self.n = self.n + 1
def stage2(self):
- self.n = self.n
+ self.n = self.n << 1
def stage3(self):
- self.n = self.n
+ self.n = ~self.n
def stage4(self):
- self._pipe.sync += self._loopback.eq(self.n)
+ self._pipe.sync += self._loopback.eq(self.n + 3)
class PipeModule(Module):
def __init__(self):