use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-library work;
-use work.glibc_random.all;
+library osvvm;
+use osvvm.RandomPkg.all;
entity random is
port (
process(clk)
variable rand : std_ulogic_vector(63 downto 0);
+ variable rnd : RandomPType;
begin
if rising_edge(clk) then
- rand := pseudorand(64);
+ rand := rnd.RandSlv(64);
data <= rand;
raw <= rand;
end if;