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[libreriscv.git] / resources.mdwn

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+++ b/resources.mdwn
@@ -25,6 +25,12 @@ This section is primarily a series of useful links found online
 
 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
 
+## OpenPOWER OpenFSI Spec (2016)
+
+* [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
+
+* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+
 # RISC-V Instruction Set Architecture
 
 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
@@ -51,9 +57,14 @@ at the moment. However, there are many wiki pages that make a reference
 to the V extension so it would be good to include it here as a reference
 for comparative/informative purposes with regard to Simple-V.
 
-## Radix MMU
+# Radix MMU
  - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
 
+# D-Cache
+
+## D-Cache Possible Optimizations papers and links
+- [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+
 
 # RTL Arithmetic SQRT, FPU etc.
 
@@ -314,6 +325,11 @@ Some learning resources I found in the community:
   1-deep / 2-register FIFO synchronizer.
 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
   Understanding Latency Hiding on GPUs, by Vasily Volkov
+* Efabless "Openlane" <https://github.com/efabless/openlane>
+* Co-simulation plugin for verilator, transferring to ECP5
+  <https://github.com/vmware/cascade>
+* Multi-read/write ported memories
+  <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
 
 
 # Real/Physical Projects
@@ -375,3 +391,20 @@ This list auto-generated from a page tag "standards":
 
 * <https://www.fed4fire.eu/testbeds/>
 
+# Really Useful Stuff
+
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
+
+# Digilent Arty
+
+* https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
+* https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
+* https://store.digilentinc.com/pmod-vga-video-graphics-array/
+* https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
+* https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
+* https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
+
+# CircuitJS experiments
+
+* [[resources/high-speed-serdes-in-circuitjs]]