[[!toc ]]
+# Getting Started
+
+This section is primarily a series of useful links found online
+
+* [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
+* Fundamentals to learn to get started [[3d_gpu/tutorial]]
+
+## Is Open Source Hardware Profitable?
+[RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
+
# OpenPOWER ISA
-* <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
-* <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
+* [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
+* [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
+
+## Overview of the user ISA:
+
+[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+
+## OpenPOWER OpenFSI Spec (2016)
+
+* [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
+
+* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
# RISC-V Instruction Set Architecture
compliant with the RISC-V standards. Doing so will allow us to to reuse
most software as-is and avoid major forks.
-* Official compiled PDFs of RISC-V ISA Manual:
- <https://github.com/riscv/riscv-isa-manual/releases/latest>
-* Working draft of the proposed RISC-V Bitmanipulation extension:
- <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf>
-* RISC-V "V" Vector Extension:
- <https://riscv.github.io/documents/riscv-v-spec/>
+* [Official compiled PDFs of RISC-V ISA Manual]
+ (https://github.com/riscv/riscv-isa-manual/releases/latest)
+* [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
+* [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
+* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
Note: As far as I know, we aren't using the RISC-V V Extension directly
at the moment. However, there are many wiki pages that make a reference
to the V extension so it would be good to include it here as a reference
for comparative/informative purposes with regard to Simple-V.
-# IEEE Standard for Floating-Point Arithmetic (IEEE 754)
+# Radix MMU
+ - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
+
+# D-Cache
+
+## D-Cache Possible Optimizations papers and links
+- [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+
+
+# RTL Arithmetic SQRT, FPU etc.
+
+## Sqrt
+* [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
+* [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
+
+## CORDIC and related algorithms
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
+* <https://bugs.libre-soc.org/show_bug.cgi?id=208>
+* [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
+* [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
+ - Does not have an easy way of computing tan(x)
+* [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
+* [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
+* <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
+
+## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
Almost all modern computers follow the IEEE Floating-Point Standard. Of
course, we will follow it as well for interoperability.
access. However, each of the Libre RISC-V members already have access
to the document.
+* [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
+
+Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
+
+* [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
+
+Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
+
+## Past FPU Mistakes to learn from
+
+* [Intel Underestimates Error Bounds by 1.3 quintillion on
+Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
+* [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
+
# Khronos Standards
The Khronos Group creates open standards for authoring and acceleration
Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
switching between different accuracy levels, in userspace applications.
-**SPIR-V Main Page <https://www.khronos.org/registry/spir-v/>**
+[**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
+
+* [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
+* [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
+* [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
-* SPIR-V 1.5 Specification Revision 1:
- <https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html>
-* SPIR-V OpenCL Extended Instruction Set:
- <https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html>
-* SPIR-V GLSL Extended Instruction Set:
- <https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html>
+[**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
-**Vulkan Main Page <https://www.khronos.org/registry/vulkan/>**
+* [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
-* Vulkan 1.1.122:
- <https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html>
+[**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
-**OpenCL Main Page <https://www.khronos.org/registry/OpenCL/>**
+* [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
+* [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
+* [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
-* OpenCL 2.2 API Specification:
- <https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html>
-* OpenCL 2.2 Extension Specification:
- <https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html>
-* OpenCL 2.2 SPIR-V Environment Specification:
- <https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html>
+* OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
+
+* [Announcement video](https://youtu.be/h0_syTg6TtY)
+* [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
Note: We are implementing hardware accelerated Vulkan and
OpenCL while relying on other software projects to translate APIs to
<https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
+* Pixilica is heading up an initiative to create a RISC-V graphical ISA
+
+* [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
+
+
# Various POWER Communities
- [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
- I still can't figure out if this chip is POWER8 or POWER9. Please verify!
- - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/]
+ The T2080 is a POWER8 chip.
+ - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
Supporting/Raising awareness of various POWER related open projects on the FOSS
community
- [OpenPOWER](https://openpowerfoundation.org)
High performance interconnect for POWER machines. One of the big advantages
of the POWER architecture. Notably more performant than PCIE Gen4, and is
designed to be layered on top of the physical PCIE link.
+ - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
+ Truly open bi-weekly teleconference lines for anybody interested in helping
+ advance or adopting the POWER architecture.
-# Free Silicon Conference
+# Conferences
+
+## Free Silicon Conference
The conference brought together experts and enthusiasts who want to build
a complete Free and Open Source CAD ecosystem for designing analog and
* //TODO LINK TO RISC-V CONFORMANCE TEST
-## IEEE 754 Tests
+## IEEE 754 Testing/Emulation
+
+IEEE 754 has no official tests for floating-point but there are
+well-known third party tools to check such as John Hauser's TestFloat.
-IEEE 754 has no official tests for floating-point but there are several
-well-known third party tools to check such as John Hauser's SoftFloat
-and TestFloat.
+There is also his SoftFloat library, which is a software emulation
+library for IEEE 754.
* <http://www.jhauser.us/arithmetic/>
-Jacob is also making a Rust library to check IEEE 754 operations.
+Jacob is also working on an IEEE 754 software emulation library written
+in Rust which also has Python bindings:
-* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-September/002737.html>
+* Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
+* Crate: <https://crates.io/crates/simple-soft-float>
+* Autogenerated Docs: <https://docs.rs/simple-soft-float/>
A cool paper I came across in my research is "IeeeCC754++ : An Advanced
Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
Some learning resources I found in the community:
-* ZipCPU: <http://zipcpu.com/>
-
-ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: <http://zipcpu.com/tutorial/>
-
-
-* Western Digital's SweRV CPU blog (I recommend looking at all their posts): <https://tomverbeure.github.io/>
-
-<https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
-
-<https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
+* ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
+ tutorial for beginners and many exercises/quizzes/slides:
+ <http://zipcpu.com/tutorial/>
+* Western Digital's SweRV CPU blog (I recommend looking at all their
+ posts): <https://tomverbeure.github.io/>
+* <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
+* <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
## Automation
* <https://danluu.com/branch-prediction/>
-
-# Information Resources and Tutorials
-
-This section is primarily a series of useful links found online
-
-* FSiC2019 <https://wiki.f-si.org/index.php/FSiC2019>
-* Fundamentals to learn to get started [[3d_gpu/tutorial]]
-* <https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers>
-* <https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/>
-* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
+# Python RTL Tools
+
+* [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
+* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
+ An SOC builder written in Python Migen DSL. Allows you to generate functional
+ RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
+ and parameterizeable CSRs.
+* [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
+* There is a great guy, Robert Baruch, who has a good
+ [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
+ He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
+ [the code](https://github.com/RobertBaruch/n6800) and
+ [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
+ online.
+* [Minerva](https://github.com/lambdaconcept/minerva)
+ An SOC written in Python nMigen DSL
+* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
-* <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
-* Samuel's KC5 code <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
+
+# Other
+
+* <https://wiki.f-si.org/index.php/FSiC2019>
+* <https://fusesoc.net>
+* <https://www.lowrisc.org/open-silicon/>
+* <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
+* <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
+ Synchronous Resets? Asynchronous Resets? I am so confused! How will I
+ ever know which to use? by Clifford E. Cummings
+* <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
+ Clock Domain Crossing (CDC) Design & Verification Techniques Using
+ SystemVerilog, by Clifford E. Cummings
+ In particular, see section 5.8.2: Multi-bit CDC signal passing using
+ 1-deep / 2-register FIFO synchronizer.
+* <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
+ Understanding Latency Hiding on GPUs, by Vasily Volkov
+* Efabless "Openlane" <https://github.com/efabless/openlane>
+* Co-simulation plugin for verilator, transferring to ECP5
+ <https://github.com/vmware/cascade>
+* Multi-read/write ported memories
+ <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
+
+
+# Real/Physical Projects
+
+* [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
* <https://chips4makers.io/blog/>
* <https://hackaday.io/project/7817-zynqberry>
-* <https://wiki.f-si.org/index.php/FSiC2019>
-* <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
+* <https://github.com/efabless/raven-picorv32>
+* <https://efabless.com>
* <https://efabless.com/design_catalog/default>
+* <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
+* <https://mshahrad.github.io/openpiton-asplos16.html>
+
+# ASIC tape-out pricing
+
+* <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
+
+# Funding
+
* <https://toyota-ai.ventures/>
-* <https://github.com/lambdaconcept/minerva>
-* <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
-* <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
+* [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
+
+# Good Programming/Design Practices
+
+* [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
+* [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
* <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
-* <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
-* <https://mshahrad.github.io/openpiton-asplos16.html>
-* <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
-* <http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/>
-* <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
-* <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
-* <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
-* <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
+* [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
+
* <https://youtu.be/o5Ihqg72T3c>
* <http://flopoco.gforge.inria.fr/>
-* Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
+* Fundamentals of Modern VLSI Devices
+ <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
+
+# 12 skills summary
+
+* <https://www.crnhq.org/cr-kit/>
# Analog Simulation
* <http://ngspice.sourceforge.net/adms.html>
* <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
-# Libre-RISC-V Standards
+# Libre-SOC Standards
This list auto-generated from a page tag "standards":
# Server setup
-[[resources/server-setup/git-mirroring]]
+* [[resources/server-setup/web-server]]
+* [[resources/server-setup/git-mirroring]]
+* [[resources/server-setup/nagios-monitoring]]
+
+# Testbeds
+
+* <https://www.fed4fire.eu/testbeds/>
+
+# Really Useful Stuff
+
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
+
+# Digilent Arty
+
+* https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
+* https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
+* https://store.digilentinc.com/pmod-vga-video-graphics-array/
+* https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
+* https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
+* https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
+
+# CircuitJS experiments
+
+* [[resources/high-speed-serdes-in-circuitjs]]
projects / libreriscv.git / blobdiff